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    <title>LPC MicrocontrollersのトピックRe: Header for LPC4350 with two M0s</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567403#M17522</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JohnR on Fri Jan 31 06:07:28 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks for the reply.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have downloaded the LPCOpen files and found the definitions for M0App and M0SUB.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The markings on the two chips are identical, thus,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC4370FET100&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SYTK8&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;9SD12500CY&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the case with the three cores, the first two addresses are identical.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;JohnR.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:51:01 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:51:01Z</dc:date>
    <item>
      <title>Header for LPC4350 with two M0s</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567401#M17520</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JohnR on Thu Jan 30 06:59:26 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I think I might have asked this question before but did not get a reply.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is there a version of the header file, LPC43xx.h, that defines constants for both M0 coprocessors?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The one I have in my compiler (LPCXpresso v6.1.0 [Build 164] [2013-10-21] ) is &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC43xx.h&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * @version&amp;nbsp; V5&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * @date&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 9. December 2011&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; * @note&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Generated with SVDConv V2.6 Build 6c&amp;nbsp; on Friday, 09.12.2011 13:56:08&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; from CMSIS SVD File 'LPC43xxv5.xml' Version 5,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; *&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; created on Friday, 09.12.2011 21:56:03, last modified on Friday, 09.12.2011 21:56:04&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;There is no mention of a second M0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;As a second question, I have two LPC-Link 2 cards bought at the same time through Digikey. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;They seem to have different JTAG configurations.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;One shows two cores&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;0x0ba01477&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;0x4ba04477&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The other shows three cores&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;0x0ba01477&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;0x0ba01477&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;0x4ba04477&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The markings on the chips seem to be identical.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks in advance for any help, I would like to able to access the second M0i in an upcoming project.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;JohnR.&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:50:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567401#M17520</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:50:59Z</dc:date>
    </item>
    <item>
      <title>Re: Header for LPC4350 with two M0s</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567402#M17521</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by lpcxpresso-support on Fri Jan 31 04:10:00 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Suggest you look at the LPC4370 build of LPCOpen…&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fnxpfile%2Flpcopen-software-development-platform-lpc43xx-packages" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc43xx-packages&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;With regards to your chip issue, I've never seen any issue with the second M0 not showing up. I presume that both chips are marked as LPC4370 ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;LPCXpresso Support&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:51:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567402#M17521</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:51:00Z</dc:date>
    </item>
    <item>
      <title>Re: Header for LPC4350 with two M0s</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567403#M17522</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by JohnR on Fri Jan 31 06:07:28 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks for the reply.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have downloaded the LPCOpen files and found the definitions for M0App and M0SUB.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The markings on the two chips are identical, thus,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;LPC4370FET100&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;SYTK8&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;9SD12500CY&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the case with the three cores, the first two addresses are identical.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;JohnR.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:51:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567403#M17522</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:51:01Z</dc:date>
    </item>
    <item>
      <title>Re: Header for LPC4350 with two M0s</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567404#M17523</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by fzfq3m on Sat Feb 15 05:38:15 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;I have the same issue &lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fforum%2Fmissing-jtag-tap-interface-one-my-two-lpc-link-2-boards-long-post%23comment-1135324" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/forum/missing-jtag-tap-interface-one-my-two-lpc-link-2-boards-long-post#comment-1135324&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I've been scratching my head trying to get my olimex adapter working with openocd and a lpclink2 as target board! I almost throw the thing out the window&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm really hopping that this be just a soft issue (some register not set correctly) but I'm not holding my breath&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:51:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Header-for-LPC4350-with-two-M0s/m-p/567404#M17523</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:51:01Z</dc:date>
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