topic Re: Multiple Interrupts on 1 GPIO Pin in LPC Microcontrollers

Multiple Interrupts on 1 GPIO Pin

lpcware — Wed, 15 Jun 2016 20:08:03 GMT

Content originally posted in LPCWare by bilgehanparay on Tue Feb 24 01:46:25 MST 2015
I want to assign two interrupts, rising and falling edge, to one pin. The manual says:

"Edge-sensitive interrupt pins can interrupt on rising or falling edges or both." (UM10601.pdf)
Continuing to read the manual, I see different registers enable rising and falling edge interrupts. (IENR, IENF,SETENRL,SIENF etc.). So I can(?) enable both of them and have different IRQs in my code for each interrupt source.(right ?)

I don't have the mcu so I can't try and see it but I have to make a design choice based on this. Any help is appreciated.

note:
LPC812M101JDH20FP is the mcu I'm planning to use.

Thanks

bilge

Re: Multiple Interrupts on 1 GPIO Pin

lpcware — Wed, 15 Jun 2016 20:08:04 GMT

Content originally posted in LPCWare by HCTEK on Tue Feb 24 01:59:42 MST 2015
Hello,

from my experience you need to use the same IRQ for that interrupt and differentiate which situation fired that interrupt. As example, there are one IRQ for DMA and you need to know which channel was interrupted.

Best Regards

Re: Multiple Interrupts on 1 GPIO Pin

lpcware — Wed, 15 Jun 2016 20:08:05 GMT

Content originally posted in LPCWare by bilgehanparay on Tue Feb 24 02:04:19 MST 2015
Thank you, yes I have seen it now from the manual. I have one IRQ for one pin.

Looks like there are two registers, FALL and RISE, to identify which interrupt source was fired(rising or falling). So I should be able to check these register in my IRQ handler function to decide if it was rising or falling edge. (right?)

Re: Multiple Interrupts on 1 GPIO Pin

lpcware — Wed, 15 Jun 2016 20:08:05 GMT

Content originally posted in LPCWare by HCTEK on Tue Feb 24 02:25:19 MST 2015
Yes ;). For GPIO, the FALL and RISE registers tells what you need.

When you start to test your micro, go to the LPCOpen examples to see how to use and configure GPIO.