<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックLPC43xx GPIO Group Interrupt</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-GPIO-Group-Interrupt/m-p/566227#M17261</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by an.kh. on Fri Apr 12 02:25:48 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;P&gt;Hello! I need to receive pin change interrupts from many pins. 8 GPIO pin interrupts are not enough.&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;How the GPIO group interrupt works? I have tested it anf found the following: active levels for enabled pins goes to AND or OR element, then directly to interrupt or by using edge detector. Is this correct? For example: 2 pins are configured to low level, group interrupt to OR+EDGE. First pin goes low - interrupt rises. Then second pin goes low (with 1st low also) - interrupt will not rise because OR chema already gives 1 and there is no edge.&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;Is there any way to implement pin change interrupts in LPC43xx like it were in LPC13xx or LPC17xx?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:51:32 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:51:32Z</dc:date>
    <item>
      <title>LPC43xx GPIO Group Interrupt</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-GPIO-Group-Interrupt/m-p/566227#M17261</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by an.kh. on Fri Apr 12 02:25:48 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;P&gt;Hello! I need to receive pin change interrupts from many pins. 8 GPIO pin interrupts are not enough.&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;How the GPIO group interrupt works? I have tested it anf found the following: active levels for enabled pins goes to AND or OR element, then directly to interrupt or by using edge detector. Is this correct? For example: 2 pins are configured to low level, group interrupt to OR+EDGE. First pin goes low - interrupt rises. Then second pin goes low (with 1st low also) - interrupt will not rise because OR chema already gives 1 and there is no edge.&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;Is there any way to implement pin change interrupts in LPC43xx like it were in LPC13xx or LPC17xx?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:51:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-GPIO-Group-Interrupt/m-p/566227#M17261</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:51:32Z</dc:date>
    </item>
  </channel>
</rss>

