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    <title>LPC Microcontrollersのトピックdual core DMA restriction?</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/dual-core-DMA-restriction/m-p/565886#M17185</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jpplus on Sun Jan 11 22:04:19 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi all,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; I have an audio application running on LPC4337. The I2S and SGPIO will be configured to trigger DMA both on M0 and M4. As I need access DMA controller from two cores, my question are:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1) can chip&amp;nbsp; genereates DMA interrupt for DUAL core in same time? &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2) can I init the DMA controller in one core and use that and generate interrupt in another core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;3) can IS2 is init in one core and generate DMA interrupt in another core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I think DMA only need to be init in one core as there is only one DMA hardware, but can be directly operated from both core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am new to this chip, but hope to get some hints on this two core DMA stuff.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; thanks&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:49:03 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:49:03Z</dc:date>
    <item>
      <title>dual core DMA restriction?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/dual-core-DMA-restriction/m-p/565886#M17185</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jpplus on Sun Jan 11 22:04:19 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi all,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; I have an audio application running on LPC4337. The I2S and SGPIO will be configured to trigger DMA both on M0 and M4. As I need access DMA controller from two cores, my question are:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1) can chip&amp;nbsp; genereates DMA interrupt for DUAL core in same time? &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2) can I init the DMA controller in one core and use that and generate interrupt in another core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;3) can IS2 is init in one core and generate DMA interrupt in another core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I think DMA only need to be init in one core as there is only one DMA hardware, but can be directly operated from both core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I am new to this chip, but hope to get some hints on this two core DMA stuff.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; thanks&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:49:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/dual-core-DMA-restriction/m-p/565886#M17185</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:49:03Z</dc:date>
    </item>
    <item>
      <title>Re: dual core DMA restriction?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/dual-core-DMA-restriction/m-p/565887#M17186</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;I'd like to bump this discussion up as I'm curious about the same thing.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 03 Oct 2017 16:38:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/dual-core-DMA-restriction/m-p/565887#M17186</guid>
      <dc:creator>nos1989</dc:creator>
      <dc:date>2017-10-03T16:38:08Z</dc:date>
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