can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

lpcware — Wed, 15 Jun 2016 20:04:32 GMT

Content originally posted in LPCWare by uratan on Tue Oct 21 07:37:55 MST 2014
Hi all.

I am trying LPC810, it is fun to handle this powerfull small-package-computer.
I am evaluating Power-profile-API-ROM-driver Now, and I have found a problem.

With IRC:12MHz and set_pll() API,
I can tune system-clock to 24MHz/36MHz, but 30MHz.

Parameters like below returns status: 0x03
  cmd[0] = 12 * 1000;
  cmd[1] = 30 * 1000;
  cmd[2] = CPU_FREQ_EQU;
  cmd[3] = 0;
  LPC_PWRD_API->set_pll(cmd, resp);
   ==> resp[0] is: 0x03 (PLL_FREQ_NOT_FOUND)
   ==> resp[1] is: 12*1000
   ==> 00000000 =SYSPLLCTRL
   ==> 00000000 =SYSPLLSTAT
   ==> 00000001 =SYSAHBCLKDIV
   ==> 0000EDF0 =PDRUNCFG

Parameters like below returns status: 0x00, and the PLL is set to 24MHz.
  cmd[0] = 12 * 1000;
  cmd[1] = 30 * 1000;
  cmd[2] = CPU_FREQ_LTE;
  cmd[3] = 0;
  LPC_PWRD_API->set_pll(cmd, resp);
   ==> resp[0] is: 0x00 (PLL_CMD_SUCCESS)
   ==> resp[1] is: 24*1000
   ==> 00000041 =SYSPLLCTRL
   ==> 00000001 =SYSPLLSTAT
   ==> 00000001 =SYSAHBCLKDIV
   ==> 0000ED70 =PDRUNCFG

Parameters like below returns status: 0x00, and the PLL is set to 36MHz !!.
  cmd[0] = 12 * 1000;
  cmd[1] = 30 * 1000;
  cmd[2] = CPU_FREQ_GTE;
  cmd[3] = 0;
  LPC_PWRD_API->set_pll(cmd, resp);
   ==> resp[0] is: 0x00 (PLL_CMD_SUCCESS)
   ==> resp[1] is: 36*1000
   ==> 00000042 =SYSPLLCTRL
   ==> 00000001 =SYSPLLSTAT
   ==> 00000001 =SYSAHBCLKDIV
   ==> 0000ED70 =PDRUNCFG

I confirmed the result by that I can communicate by uart correctly
and register values dumped thru the uart.

My LPC810 is:

    /*
     *   +------------+
     *   | LPC810     |
     *   ) P  M021F   |
     *   ) X  1M28603 |
     *   | N  +D3414C | ... year 3, week 41, 4C' ver.13.4
     *   +------------+
     *      | Dev.ID:  0x00008100
     *      | B.L.Ver: 13.4         <-- by FlashMagic
     */

And referecing:

    /*
     *   UM10601: LPC81x User manual Rev.1.6
     *   LPC81xM: Product data sheet Rev.4.3
     *   lpcopen_2_01_lpcxpresso_nxp_lpcxpresso_812.zip
     */

I want to use sysCLK=30MHz from IRC:12MHz, shall I not use set_pll() ROM-API ?

- * - * -

p.s.
     Some mistakes in UM10601(Rev.1.6) are found, please confirm these.
(1) Page.127 of 370: PINENABLE0 description
wrong:   ACMP_I0/ACMP_I1
correct: ACMP_I1/ACMP_I2
(2) Page.27 of 370: Reset value of WDTOSCCTRL
wrong:   0x0A0
correct: 0x000

Re: can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

lpcware — Wed, 15 Jun 2016 20:04:33 GMT

Content originally posted in LPCWare by NXP_Paul on Wed Oct 22 11:44:04 MST 2014
Hello
I confirmed your findings, and am now investigating why a 30MHz system clock cannot be obtained using the set_pll() ROM-API function. While I investigate this, you can obtain the 30 MHz clock by using the following values in system_LPC8xx.c:

#define CLOCK_SETUP           1
#define SYSOSCCTRL_Val        0x00000000              // Reset: 0x000
#define WDTOSCCTRL_Val        0x00000000              // Reset: 0x000
#define SYSPLLCTRL_Val        0x00000024              // Reset: 0x000
#define SYSPLLCLKSEL_Val      0x00000000              // Reset: 0x000
#define MAINCLKSEL_Val        0x00000003              // Reset: 0x000
#define SYSAHBCLKDIV_Val      0x00000002              // Reset: 0x001

Regards
Paul

Re: can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

lpcware — Wed, 15 Jun 2016 20:04:33 GMT

Content originally posted in LPCWare by uratan on Sun Oct 26 05:49:55 MST 2014
Thank you for your comment.
I will continue to evaluate 'set_power' ROM-API function, with your advice.

LPC MicrocontrollersのトピックRe: can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

Re: can not configure PLL for sysCLK=30MHz by set_pll() ROM-API

Re: can not configure PLL for sysCLK=30MHz by set_pll() ROM-API