CCLK and SDRAM DynamicRefresh

lpcware — Wed, 15 Jun 2016 17:23:23 GMT

Content originally posted in LPCWare by FrankAndersen on Thu Jul 18 05:48:43 MST 2013
Hi,

I am trying to reduce the CCLK in order to save power, but I am concerned that the SDRAM will suffer from this, as the EMC CLK is equal to CCLK.

Is it okay to change the Dynamic Refresh Register on the fly?

Basicly I am doing this:

    if ( Mode == POWER_SAVE )
    {
        LPC_EMC->DynamicRefresh    = 0x00000023; /* ( n * 16 ) -> 560 clock cycles -> 15.560uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */
        LPC_SC->CCLKSEL = 0x104; // Set Clk to 36 MHz
    }
    else
    {
      LPC_SC->CCLKSEL = 0x102; // Set Clk to 48 MHz
      LPC_EMC->DynamicRefresh    = 0x00000046; /* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */
    }

Are there anything else I have to change to the EMC for the SDRAM?

Best regards,

Frank Andersen

LPC MicrocontrollersのトピックCCLK and SDRAM DynamicRefresh

CCLK and SDRAM DynamicRefresh