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    <title>LPC MicrocontrollersのトピックLPC54102 mail box interrupt on NVIC after wake up from Deep_Sleep or Power_Down</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-mail-box-interrupt-on-NVIC-after-wake-up-from-Deep/m-p/563964#M16787</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am investigating the LPC54102 chip and try to find out the mailbox function with the LPC Open examples and heart rate monitor example.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When I enable the NVIC MAILBOX_IRQn and create the interrupt handler for MAILBOX in the heartrate M0+ example, the MAILBOX_IRQn seems triggering whenever the device is waking up from the Deep_Sleep or Power_Down mode in addition to appropriate timing.&lt;/P&gt;&lt;P&gt;It is working as intended when the low power mode is set to the sleep mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could somebody explain why Mailbox interrupt triggers with Deep_Sleep or Power_Down and does not trigger with sleep mode and suggests some methods to avoid triggering MAILBOX_IRQn, other than disabling the MAILBOX_IRQn?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for help in advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 02 Aug 2016 22:33:32 GMT</pubDate>
    <dc:creator>knishi</dc:creator>
    <dc:date>2016-08-02T22:33:32Z</dc:date>
    <item>
      <title>LPC54102 mail box interrupt on NVIC after wake up from Deep_Sleep or Power_Down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-mail-box-interrupt-on-NVIC-after-wake-up-from-Deep/m-p/563964#M16787</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I am investigating the LPC54102 chip and try to find out the mailbox function with the LPC Open examples and heart rate monitor example.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;When I enable the NVIC MAILBOX_IRQn and create the interrupt handler for MAILBOX in the heartrate M0+ example, the MAILBOX_IRQn seems triggering whenever the device is waking up from the Deep_Sleep or Power_Down mode in addition to appropriate timing.&lt;/P&gt;&lt;P&gt;It is working as intended when the low power mode is set to the sleep mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could somebody explain why Mailbox interrupt triggers with Deep_Sleep or Power_Down and does not trigger with sleep mode and suggests some methods to avoid triggering MAILBOX_IRQn, other than disabling the MAILBOX_IRQn?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank you for help in advance.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Aug 2016 22:33:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-mail-box-interrupt-on-NVIC-after-wake-up-from-Deep/m-p/563964#M16787</guid>
      <dc:creator>knishi</dc:creator>
      <dc:date>2016-08-02T22:33:32Z</dc:date>
    </item>
    <item>
      <title>Re: LPC54102 mail box interrupt on NVIC after wake up from Deep_Sleep or Power_Down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-mail-box-interrupt-on-NVIC-after-wake-up-from-Deep/m-p/563965#M16788</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;Hello Knishi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Mailbox IRQ is triggered&amp;nbsp;by internal code by writting non-zero values to IRQ0/IRQ1 registers, but not by external events, so in principle during deep sleep or power down, mailbox IRQ can't happen.&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If Mailbox IRQ is entered on wake up, you can check&lt;/P&gt;&lt;P&gt;1. which core enters mailbox IRQ,&lt;/P&gt;&lt;P&gt;2. the IRQ0/IRQ1 values to confirm if the IRQ is triggered by software (Don't forget to clear&amp;nbsp;IRQ0/IRQ1 to 0&amp;nbsp;in mailbox ISR).&amp;nbsp;&lt;/P&gt;&lt;P&gt;3. The value of CPU core's IPSR register to see if it is indeed the mailbox IRQ (Cortex-M4 has a known issue that makes the core fetching wrong vector in a rare&amp;nbsp;case).&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Here is a quick workaround&amp;nbsp;before locating the root cause: make sure IRQ0/IRQ1 are cleared in mailbox ISR, and if mailbox IRQ occurs, check the IRQ0/IRQ1 values, if the values can't be recognized then ignore the mailbox IRQ.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can check multicore examples in LPCOpen for more details,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Hope this helps!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regars&lt;/P&gt;&lt;P&gt;Isaac&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 29 Aug 2016 17:16:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC54102-mail-box-interrupt-on-NVIC-after-wake-up-from-Deep/m-p/563965#M16788</guid>
      <dc:creator>isaacavila</dc:creator>
      <dc:date>2016-08-29T17:16:04Z</dc:date>
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