<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC MicrocontrollersのトピックRe: LPC43xx - maximum external memory size</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563452#M16678</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;UL&gt;&lt;LI&gt;Using SPIFI address 0x8000 0000 allows for a 128MByte qSPI flash&lt;/LI&gt;&lt;LI&gt;1GBit SDRAM is possible as a 32M x 32 as shown in the users manual. But&amp;nbsp;I only know these SDRAMs as mobile SDRAM with a 1.8V interface, working with level shifters is not possible. So finally you end up with 512MBit devices as maximum memory size in one chip. But you could place 4 of them on DYCS[3:0].&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;NXP Support Team&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 26 Aug 2016 10:41:47 GMT</pubDate>
    <dc:creator>bernhardfink</dc:creator>
    <dc:date>2016-08-26T10:41:47Z</dc:date>
    <item>
      <title>LPC43xx - maximum external memory size</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563451#M16677</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I'm looking for confirmation of the maximum external memory sizes that can be used with the LPC43xx controllers (with a single chip).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Per&amp;nbsp;UM10503:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;SDRAM&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;(23.3 Features):&lt;/STRONG&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;16-bit and 32-bit wide chip select SDRAM memory support with up to four chip selects&lt;BR /&gt;and up to 256 MB of data.&lt;BR /&gt;• Controller supports 2 kbit, 4 kbit, and 8 kbit row address synchronous memory parts.&lt;BR /&gt;That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per&lt;BR /&gt;device.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;STRONG&gt;But (Table 434):&lt;/STRONG&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;1 Gb (32Mx32)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;So is the max for&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;SDRAM at the EMC&lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;STRONG&gt;128 Mbyte (1Gb) or&lt;/STRONG&gt;&lt;/LI&gt;&lt;LI&gt;&lt;STRONG&gt;512 Mbyte (using DYCS2+DYCS3, I guess?)&lt;/STRONG&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;SPIFI (Table 445.):&lt;/STRONG&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;SPIFI data 0x1400 0000 to 0x17FF FFFF (Use this memory area for debugging code and for&lt;BR /&gt;slightly improved performance).&lt;BR /&gt;0x8000 0000 to 0x87FF FFFF (Debug will not work if the program counter is in this&lt;BR /&gt;memory area).&lt;BR /&gt;Remark: These are the spaces allocated to the SPIFI in the LPC43xx. The same&lt;BR /&gt;data appears in the first area and the first half of the second area. These areas&lt;BR /&gt;allow up to 64 MB and up to 128 MB of SPI flash to be mapped into the Cortex-M4&lt;BR /&gt;memory space. In practice, the usable space is limited to the size of the connected&lt;BR /&gt;device.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;And for&amp;nbsp;Serial Flash at the SPIFI,&amp;nbsp;the maximal&amp;nbsp;addressable/usable memory size is &lt;/STRONG&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;&lt;STRONG&gt;128 Mbyte?&lt;/STRONG&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Aug 2016 01:13:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563451#M16677</guid>
      <dc:creator>zzzmqp</dc:creator>
      <dc:date>2016-08-26T01:13:28Z</dc:date>
    </item>
    <item>
      <title>Re: LPC43xx - maximum external memory size</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563452#M16678</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;UL&gt;&lt;LI&gt;Using SPIFI address 0x8000 0000 allows for a 128MByte qSPI flash&lt;/LI&gt;&lt;LI&gt;1GBit SDRAM is possible as a 32M x 32 as shown in the users manual. But&amp;nbsp;I only know these SDRAMs as mobile SDRAM with a 1.8V interface, working with level shifters is not possible. So finally you end up with 512MBit devices as maximum memory size in one chip. But you could place 4 of them on DYCS[3:0].&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;NXP Support Team&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Aug 2016 10:41:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563452#M16678</guid>
      <dc:creator>bernhardfink</dc:creator>
      <dc:date>2016-08-26T10:41:47Z</dc:date>
    </item>
    <item>
      <title>Re: LPC43xx - maximum external memory size</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563453#M16679</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Excellent, thank you &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/bernhardfink"&gt;bernhardfink&lt;/A&gt;‌!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 26 Aug 2016 13:20:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC43xx-maximum-external-memory-size/m-p/563453#M16679</guid>
      <dc:creator>zzzmqp</dc:creator>
      <dc:date>2016-08-26T13:20:29Z</dc:date>
    </item>
  </channel>
</rss>

