LPC MicrocontrollersのトピックRe: Unstable RAM access after changing speed to 204MHz

Unstable RAM access after changing speed to 204MHz

lpcware — Wed, 15 Jun 2016 18:47:09 GMT

Content originally posted in LPCWare by Jon Reece on Wed Mar 27 02:36:30 MST 2013
Hi,

I am using an EA OEM board for an application and I am trying to increase the speed of the processor to reduce the processing time. I have successfully changed the clock speed in steps following the BlickFast example. When I query the clock speed I now get 204000000 as expected. However, when I try and access the SDRAM the processor will disconnect from the debugger and I cannot stop/reprogram it.

Do you have an example of setting up the SDRAM peripheral to work at 102MHz with a core clock of 204MHz? The ISSI RAM chip that we are using, IS42S32800D-6BLI, should support bus speeds of upto 166MHz so I don't believe that 102MHz should be a problem. I am using the NS2CLK function to get the register timing values which implies that I should be able to change the clock speed and the ram *should* (as I understand it) work.

If you need any more information please let me know,

Thanks
Jon

Re: Unstable RAM access after changing speed to 204MHz

lpcware — Wed, 15 Jun 2016 18:47:10 GMT

Content originally posted in LPCWare by suckfish on Mon Apr 01 15:59:30 MST 2013
Everything locking up when you access SDRAM could well be a clocking problem.

Check that you have all 4 EMC clock outs going to the pins, and that you have the *input* buffers enabled on those pins also.

[It's counter-intuitive that you need all 4, and that you need them as inputs also, but yes you do. Presumably the EMC is using the inputs as feedback to adjust timing.]

Re: Unstable RAM access after changing speed to 204MHz

lpcware — Wed, 15 Jun 2016 18:47:11 GMT

Content originally posted in LPCWare by larsjep on Wed Apr 03 02:10:38 MST 2013
Hi,

Please notice that LPC43xx has a problem with the EMC clock divider.
When the clock divider is enabled the duty cycle of the EMC clock is not 50%
This can result in problems with the required setup times of the address signals.

Regards
Lars

Re: Unstable RAM access after changing speed to 204MHz

lpcware — Wed, 15 Jun 2016 18:47:11 GMT

Content originally posted in LPCWare by hlsa on Fri Apr 19 02:36:55 MST 2013

This is a known problem of the EA-Board. I have already addressed this issue to EA in february and they confirmed the problem. As far as I know, there is still no solution (what a shame for EA). SDRAM works here only up to 144 MHz.

In the meantime I bought an evaluation board from Keil (MCB4357) and I do have my own hardware. On both of the SDRAM works fine.

Best regards,

Holger