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    <title>LPC Microcontrollers中的主题 How to use the grouped GPIO Interrupt on LPC4357 M0 core</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-to-use-the-grouped-GPIO-Interrupt-on-LPC4357-M0-core/m-p/560784#M16156</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Taniguchi on Tue Jul 30 04:40:02 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is there someone who can use the grouped GPIO interrupt on LPC4357 M0 core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPC4357 Dev Kit manufactured by Embedded Artists AB and trying to use the grouped GPIO interrupt block (GROUP1) on M0 core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, M0_GINT1_IRQHandler function in cr_startup_lpc43xx-m0.c is not called from NVIC if CTRL register that displying interrupt status of GROUP1 is active.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm setting the register of the grouped GPIO by the following process.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;If you find any mistakes, could you please correct them?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;--------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;// The purpose of these process is to receive interrupts&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;// from GPIO4[9] or GPIO4[12] (SW7 Joystic output - LOW active signal)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;#include "core_cm0.h"&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#include "LPC43xx.h"&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void main (void)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Clear the interrupt status of GROUP1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;CTRL |= ( 0x1 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set polarity of GPIO4[9] and GPIO4[12] to LOW active.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_POL4 &amp;amp;= ~( 0x1 &amp;lt;&amp;lt; 9 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_POL4 &amp;amp;= ~( 0x1 &amp;lt;&amp;lt; 12 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Enable GPIO4[9] and GPIO4[12] for GROUP1 interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_ENA4 |= ( 0x1 ) &amp;lt;&amp;lt; 9;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_ENA4 |= ( 0x1 ) &amp;lt;&amp;lt; 12;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set ISER register at NVIC to enable GROUP1 interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; NVIC_EnableIRQ( M0_GINT1_IRQn );&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Taniguchi&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:44:53 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:44:53Z</dc:date>
    <item>
      <title>How to use the grouped GPIO Interrupt on LPC4357 M0 core</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/How-to-use-the-grouped-GPIO-Interrupt-on-LPC4357-M0-core/m-p/560784#M16156</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Taniguchi on Tue Jul 30 04:40:02 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is there someone who can use the grouped GPIO interrupt on LPC4357 M0 core?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPC4357 Dev Kit manufactured by Embedded Artists AB and trying to use the grouped GPIO interrupt block (GROUP1) on M0 core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, M0_GINT1_IRQHandler function in cr_startup_lpc43xx-m0.c is not called from NVIC if CTRL register that displying interrupt status of GROUP1 is active.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm setting the register of the grouped GPIO by the following process.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;If you find any mistakes, could you please correct them?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;--------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;// The purpose of these process is to receive interrupts&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;// from GPIO4[9] or GPIO4[12] (SW7 Joystic output - LOW active signal)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;#include "core_cm0.h"&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;#include "LPC43xx.h"&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void main (void)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Clear the interrupt status of GROUP1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;CTRL |= ( 0x1 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set polarity of GPIO4[9] and GPIO4[12] to LOW active.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_POL4 &amp;amp;= ~( 0x1 &amp;lt;&amp;lt; 9 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_POL4 &amp;amp;= ~( 0x1 &amp;lt;&amp;lt; 12 );&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Enable GPIO4[9] and GPIO4[12] for GROUP1 interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_ENA4 |= ( 0x1 ) &amp;lt;&amp;lt; 9;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; LPC_GPIO_GROUP_INT1-&amp;gt;PORT_ENA4 |= ( 0x1 ) &amp;lt;&amp;lt; 12;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; // Set ISER register at NVIC to enable GROUP1 interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; NVIC_EnableIRQ( M0_GINT1_IRQn );&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;--------------------------------------------------------------&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Taniguchi&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:44:53 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/How-to-use-the-grouped-GPIO-Interrupt-on-LPC4357-M0-core/m-p/560784#M16156</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:44:53Z</dc:date>
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