LPC MicrocontrollersのトピックRe: JTAG debug failing -- TRST and DBGEN function

JTAG debug failing -- TRST and DBGEN function

lpcware — Wed, 15 Jun 2016 18:44:08 GMT

Content originally posted in LPCWare by aras on Mon Feb 18 14:31:23 MST 2013
Hi,

I am having trouble getting JTAG to work on a series of 6 simple prototypes. Two boards fire up, one somewhat intermittently and 3 fail always. We have an NGX 4330 xplorer board with exactly the same chip revision and that almost always connects over JTAG with Segger, Keil uLink, and Xpresso, but not with Olimex (due to capacitor on reset line/switch). We might have assembly problems, but everything else checks out to be connected fine so this seems rather unlikely/unlucky.

The part marking is:

      LPC4330FET100
      PFM906.04     05
      ESD1201ZRY

Which revision is this? -- not A or B apparently -- and what errata apply? What are the exact functions of TRST and DBGEN and their interaction? Is DBGEN latched on a reset signal? -- in other words would it be possible to have a race situation if both signals change together at startup?

Lastly, do all power domains have to be powered in order for JTAG to work on a 43xx? RTC included...

Thanks for you help, Richard.

Re: JTAG debug failing -- TRST and DBGEN function

lpcware — Wed, 15 Jun 2016 18:44:09 GMT

Content originally posted in LPCWare by nxp21346 on Mon Feb 18 15:12:33 MST 2013
DBGEN must be high to enable JTAG/SWD debugging. When DBGEN is low, JTAG boundary scan is enabled. DBGEN is not latched so it must be held high while debugging the part. The RTC domain does not need to be externally powered to enable debug.

-Dave @ NXP

Re: JTAG debug failing -- TRST and DBGEN function

lpcware — Wed, 15 Jun 2016 18:44:10 GMT

Content originally posted in LPCWare by starblue on Tue Feb 19 01:48:13 MST 2013
For the LPC4350 the marking ZRY is a marking error and indicates Revision A:

http://www.lpcware.com/content/forum/errata-situation-can-lpc4350-revision-esd1148zry#comment-2189

Re: JTAG debug failing -- TRST and DBGEN function

lpcware — Wed, 15 Jun 2016 18:44:10 GMT

Content originally posted in LPCWare by aras on Wed Feb 20 09:53:59 MST 2013
Thanks for the fast response!

So, DBGEN is level sensitive, but what clock domain does it live in? Presumably JTAG CLK. Might it be necessary to do a reset, TRST or HW reset, after changing it? Or does it have simply a static logic (ie mux) function?

I ask because on our board TRST and DBGEN are tied together (a mistake) and if I do the same thing on an Xplorer board I can sometimes repeat the errant behaviour. Are there other conditions that affect the ability of debuggers to "connect" to JTAG/SWD? We have seen this problem with all 5 of the debuggers available to us, perhaps on some more than others. We have done basic stuff like reduce the jtag clk freq. Clearly, under certain conditions, JTAG just gets jammed -- e.g. when core clock is out of spec? Can you list some of those conditions and what can be done to resolve them, please? TRST, Reset and so on?

Cheers, Richard.