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    <title>LPC MicrocontrollersのトピックDMA and SSP in LPC11Uxx</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-and-SSP-in-LPC11Uxx/m-p/560121#M16025</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The user manual of the LPC11U68 indicates that the DMA can be used with the SSP&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Table 229: SSP/SPI DMA Control Register (DMACR, address&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;RXDMAE Receive DMA Enable. When this bit is set to one 1, DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for the receive FIFO is enabled, otherwise receive DMA is&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;disabled.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1 TXDMAE Transmit DMA Enable. When this bit is set to one 1, DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for the transmit FIFO is enabled, otherwise transmit DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;is disabled&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anybody clarify what are the event which trigger the DMA RX and TX requests (Start of transfers) ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 02 Aug 2016 13:14:58 GMT</pubDate>
    <dc:creator>pberna</dc:creator>
    <dc:date>2016-08-02T13:14:58Z</dc:date>
    <item>
      <title>DMA and SSP in LPC11Uxx</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-and-SSP-in-LPC11Uxx/m-p/560121#M16025</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The user manual of the LPC11U68 indicates that the DMA can be used with the SSP&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Table 229: SSP/SPI DMA Control Register (DMACR, address&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;RXDMAE Receive DMA Enable. When this bit is set to one 1, DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for the receive FIFO is enabled, otherwise receive DMA is&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;disabled.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1 TXDMAE Transmit DMA Enable. When this bit is set to one 1, DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for the transmit FIFO is enabled, otherwise transmit DMA&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;is disabled&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Can anybody clarify what are the event which trigger the DMA RX and TX requests (Start of transfers) ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 02 Aug 2016 13:14:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-and-SSP-in-LPC11Uxx/m-p/560121#M16025</guid>
      <dc:creator>pberna</dc:creator>
      <dc:date>2016-08-02T13:14:58Z</dc:date>
    </item>
    <item>
      <title>Re: DMA and SSP in LPC11Uxx</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-and-SSP-in-LPC11Uxx/m-p/560122#M16026</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Paolo,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; I get that the LPC11U68 SPI DMA can refer to LPC82X, so the SPI DMA question should like this:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;DMA operation&lt;/P&gt;&lt;P&gt;A DMA request is provided for each SPI direction, and can be used in lieu of interrupts for transferring data by configuring the DMA controller appropriately, and enabling the Rx&lt;/P&gt;&lt;P&gt;and/or Tx DMA via the DMACR register. The DMA controller provides an acknowledgement signal that clears the related request when it completes handling that request.&lt;/P&gt;&lt;P&gt;The transmitter DMA request is asserted when Tx DMA is enabled and the transmitter can accept more data.&lt;/P&gt;&lt;P&gt;The receiver DMA request is asserted when Rx DMA is enabled and received data is available to be read.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; Besides the SPI FIFO as the DMA request, DMA trigger also can start the SPI transfer, for details, please refer to the DMA chapter about the trigger.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Wish it helps you!&lt;/P&gt;&lt;P&gt;If you still have question, please let me know!&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Jingjing&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 08 Aug 2016 10:03:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-and-SSP-in-LPC11Uxx/m-p/560122#M16026</guid>
      <dc:creator>kerryzhou</dc:creator>
      <dc:date>2016-08-08T10:03:10Z</dc:date>
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