LCD Controller

lpcware — Wed, 15 Jun 2016 18:42:32 GMT

Content originally posted in LPCWare by bunrockter on Thu Sep 06 23:46:24 MST 2012
Does anyone know if the clocks per line setting in the LCD control register is supposed to include the front & back porch for a TFT display. The User manual says:

This field specifies the number of actual LCDDCLK clocks to the
LCD panel on each line. This is the number of PPL divided by
either 1 (for TFT)

Which would make me believe that it is just the active area, but is it actually supposed to be the active area plus the front & back porches?

Thanks,

Bun

Re: LCD Controller

lpcware — Wed, 15 Jun 2016 18:42:33 GMT

Content originally posted in LPCWare by bunrockter on Thu Sep 06 23:47:49 MST 2012
Sorry the Clock and Signal Polarity register, not the control register (POL->25:16 (CPL))

Re: LCD Controller

lpcware — Wed, 15 Jun 2016 18:42:33 GMT

Content originally posted in LPCWare by bunrockter on Wed Sep 26 17:36:22 MST 2012
Well, I got my LCD up & running, I may be wrong, but it seems that the cloks per line is just the number of pixels per line (active area). When I added in the back and front porches my image gets shifted. Then again I also have to do some funny timing tricks with the back porch so that may be comming in to play as well.

Re: LCD Controller

lpcware — Wed, 15 Jun 2016 18:42:34 GMT

Content originally posted in LPCWare by Dave on Thu Sep 27 12:31:12 MST 2012
You are correct...

it's the number of pixels per line, minus 1, for standard TFT...

If you're using a 4 bit mono, then it's pixels/4, minus 1...

If you're using an 8 bit mono, then it's pixels/8, minus 1...

and if you're using an STN, then it's pixels*3/8, minus 1....

Here's an example:

<code>
   regValue = 0x00000000;              // start out with zero...

   // ------------------------------------------------------------------------------------------
   // BITS 4:0 Panel Clock Divisor
   // Find the dot clock divider with the fastest clock rate to match the requested
   // dot clock rate without going over.
   // ------------------------------------------------------------------------------------------
   for( Divisor=0; Divisor<0x0F; Divisor++ )
      {
      if( (SystemCoreClock/(Divisor+2)) <= DefaultDisplay.iDotClockHz )
         break;
      }
    regValue |= Divisor;               // update value...

   // ------------------------------------------------------------------------------------------
   // BIT 5 Clock Select - always 0...
   // BITS 10:6 AC bias pin frequency - not for TFT displays, so leave 0
   // ------------------------------------------------------------------------------------------

   // ------------------------------------------------------------------------------------------
   // BIT 11 Invert vertical synchronization
   // ------------------------------------------------------------------------------------------
   if(DefaultDisplay.iInvertVerticalSync)
      regValue |= (1<<11);

   // ------------------------------------------------------------------------------------------
   // BIT 12 Invert horizontal synchronization
   // ------------------------------------------------------------------------------------------
   if(DefaultDisplay.iInvertHorizontalSync)
      regValue |= (1<<12);

   // ------------------------------------------------------------------------------------------
   // BIT 13 Invert panel clock
   // ------------------------------------------------------------------------------------------
   if(DefaultDisplay.iInvertPanelClock)
      regValue |= (1<<13);

   // ------------------------------------------------------------------------------------------
   // BIT 14 Invert output enable
   // ------------------------------------------------------------------------------------------
   if(DefaultDisplay.iInvertOutputEnable)
      regValue |= (1<<14);

   // ------------------------------------------------------------------------------------------
   // BITS 25:16 Clocks per line
   // ------------------------------------------------------------------------------------------
   switch( DefaultDisplay.iPanelType )
      {
      case LCD_STANDARD_TFT:
      case LCD_ADVANCED_TFT:
      case LCD_HIGHLY_REFLECTIVE_TFT:
      default:
         regValue |= (((DefaultDisplay.iHorizontalPixelsPerLine-1) & 0x3FF) << 16);
         break;
      case LCD_4BIT_MONO:
         regValue |= ((((DefaultDisplay.iHorizontalPixelsPerLine / 4)-1) & 0x3FF) << 16);
         break;
      case LCD_8BIT_MONO:
         regValue |= ((((DefaultDisplay.iHorizontalPixelsPerLine / 8)-1) & 0x3FF) << 16);
         break;
      case LCD_COLOR_STN:
         regValue |= (((((DefaultDisplay.iHorizontalPixelsPerLine * 3)/8)-1) & 0x3FF) << 16);
         break;
      }

   // ------------------------------------------------------------------------------------------
   // BIT 26 Bypass pixel clock divider - always 0...
   // BITS 31:27 Upper five bits of panel clock divisor - the TFT divisor is never more than 15,
   //            so these will always be zero...
   // ------------------------------------------------------------------------------------------
    LPC_LCD->POL = regValue;
</code>

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