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    <title>LPC MicrocontrollersのトピックDMA Link mode on 54102</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-Link-mode-on-54102/m-p/559009#M15730</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jfavaro on Thu Jan 21 03:05:22 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;i'm trying to set up the 54102 to obtain an DMA linked memory to memory transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;this is the code i used just to try a simple memory to memory transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Using the debbugger i can see that the first transfer is correcty completed but the second one never start.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;TxTest=0xA0A0A0A0;
RxTest=0;
RxTest1=0;

dmaDesc.source = DMA_ADDR((&amp;amp;TxTest));
//dmaDesc.dest = DMA_ADDR((&amp;amp;(LPC_SPIMASTERPORT-&amp;gt;TXDATCTL)));

dmaDesc.dest = DMA_ADDR((&amp;amp;RxTest));
dmaDesc.next = DMA_ADDR(&amp;amp;(dmaDesc1));



dmaDesc1.xfercfg =(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 |DMA_XFERCFG_SETINTA | DMA_XFERCFG_CLRTRIG&amp;nbsp; );
//dmaDesc1.source = DMA_ADDR(&amp;amp;(LPC_SPIMASTERPORT-&amp;gt;RXDAT));
dmaDesc1.source = DMA_ADDR((&amp;amp;TxTest));

dmaDesc1.dest = DMA_ADDR(&amp;amp;RxTest1);


dmaDesc1.next= DMA_ADDR(0);


NVIC_EnableIRQ(DMA_IRQn);




/* Setup transfer descriptor and validate it */
Chip_DMA_SetupTranChannel(LPC_DMA, DMA_CH0, &amp;amp;dmaDesc);
Chip_DMA_SetValidChannel(LPC_DMA, DMA_CH0);
Chip_DMA_SetupChannelTransfer(LPC_DMA, DMA_CH0,(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 )); //
/* Setup data transfer and software trigger in same call */
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;the structure i used for the descriptor is the default one used also in the DMA example &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;typedef struct {
uint32_t&amp;nbsp; xfercfg;/*!&amp;lt; Transfer configuration (only used in linked lists and ping-pong configs) */
uint32_t&amp;nbsp; source;/*!&amp;lt; DMA transfer source end address */
uint32_t&amp;nbsp; dest;/*!&amp;lt; DMA transfer desintation end address */
uint32_t&amp;nbsp; next;/*!&amp;lt; Link to next DMA descriptor, must be 16 byte aligned */
} DMA_CHDESC_T;&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Any suggest ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:58:10 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:58:10Z</dc:date>
    <item>
      <title>DMA Link mode on 54102</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-Link-mode-on-54102/m-p/559009#M15730</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by jfavaro on Thu Jan 21 03:05:22 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;i'm trying to set up the 54102 to obtain an DMA linked memory to memory transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;this is the code i used just to try a simple memory to memory transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Using the debbugger i can see that the first transfer is correcty completed but the second one never start.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;TxTest=0xA0A0A0A0;
RxTest=0;
RxTest1=0;

dmaDesc.source = DMA_ADDR((&amp;amp;TxTest));
//dmaDesc.dest = DMA_ADDR((&amp;amp;(LPC_SPIMASTERPORT-&amp;gt;TXDATCTL)));

dmaDesc.dest = DMA_ADDR((&amp;amp;RxTest));
dmaDesc.next = DMA_ADDR(&amp;amp;(dmaDesc1));



dmaDesc1.xfercfg =(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 |DMA_XFERCFG_SETINTA | DMA_XFERCFG_CLRTRIG&amp;nbsp; );
//dmaDesc1.source = DMA_ADDR(&amp;amp;(LPC_SPIMASTERPORT-&amp;gt;RXDAT));
dmaDesc1.source = DMA_ADDR((&amp;amp;TxTest));

dmaDesc1.dest = DMA_ADDR(&amp;amp;RxTest1);


dmaDesc1.next= DMA_ADDR(0);


NVIC_EnableIRQ(DMA_IRQn);




/* Setup transfer descriptor and validate it */
Chip_DMA_SetupTranChannel(LPC_DMA, DMA_CH0, &amp;amp;dmaDesc);
Chip_DMA_SetValidChannel(LPC_DMA, DMA_CH0);
Chip_DMA_SetupChannelTransfer(LPC_DMA, DMA_CH0,(DMA_XFERCFG_CFGVALID | DMA_XFERCFG_WIDTH_32 )); //
/* Setup data transfer and software trigger in same call */
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;the structure i used for the descriptor is the default one used also in the DMA example &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;typedef struct {
uint32_t&amp;nbsp; xfercfg;/*!&amp;lt; Transfer configuration (only used in linked lists and ping-pong configs) */
uint32_t&amp;nbsp; source;/*!&amp;lt; DMA transfer source end address */
uint32_t&amp;nbsp; dest;/*!&amp;lt; DMA transfer desintation end address */
uint32_t&amp;nbsp; next;/*!&amp;lt; Link to next DMA descriptor, must be 16 byte aligned */
} DMA_CHDESC_T;&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Any suggest ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:58:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-Link-mode-on-54102/m-p/559009#M15730</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:58:10Z</dc:date>
    </item>
    <item>
      <title>Re: DMA Link mode on 54102</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-Link-mode-on-54102/m-p/559010#M15731</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mckenney on Sat Mar 05 10:20:10 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;This is from the LPC824, but the two DMA engines look similar:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I recall I had to explicitly clear the completion status (INTA in your case) from the previous operation in order for a new operation to start. The symptom was what you describe: It just sat there and didn't start.&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:58:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/DMA-Link-mode-on-54102/m-p/559010#M15731</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:58:11Z</dc:date>
    </item>
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