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    <title>topic Re: M0+ not working when M4 goes in deep sleep mode in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558106#M15549</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by nerd herd on Fri Jul 10 17:08:52 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: filartrix&lt;/STRONG&gt;&lt;BR /&gt;I read someone asking whether is possible to let the M0 behave as master, could this be a solution?&lt;BR /&gt;or am I missing something?&lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: embd02161991&lt;/STRONG&gt;&lt;BR /&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;The Deep-sleep and power-down modes affect the entire system. In both modes, the clock to all CPUs is shut down and the peripherals receive no internal clocks. So both M0+ and M4 will not have clock in Deep sleep and power down modes.&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;BR /&gt;NXP Technical Support&lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For clarity, I would like to add onto this answer by saying that making the M0+ core a master will not change anything. &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:58:03 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:58:03Z</dc:date>
    <item>
      <title>M0+ not working when M4 goes in deep sleep mode</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558104#M15547</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by filartrix on Fri Jul 10 06:46:59 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi all, &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;my purpose is to have the M0 running, while the M4 is in "POWER_DEEP_SLEEP" or "POWER_POWER_DOWN".&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I started from multicore blinky project and made the following modifications:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- removed any reference to mailboxes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- set the clock source to IRC clock and turned of PLL&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;- added systick ISR and configuration to M0 code to led a led blink (the LED is thus driven by the M0+)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;here's an extract of the M4 code:&lt;/SPAN&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;int main(void)
{
uint32_t *jumpAddr, *stackAddr;

SystemCoreClockUpdate();
Board_Init();
setupClocking(); // Turn off PLL sent IRC as clock source
SystemCoreClockUpdate(); //MCU now runs @12MHz

&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; stackAddr = (uint32_t *) (*(uint32_t *) M0_BOOT_STACKADDR);
jumpAddr = (uint32_t *) (*(uint32_t *) M0_BOOT_ENTRYADDR);
Chip_CPU_CM0Boot(jumpAddr, stackAddr);&amp;nbsp; //Boot the M0

&amp;nbsp;&amp;nbsp;&amp;nbsp; POWER_MODE_T powerMode&amp;nbsp; = POWER_DEEP_SLEEP;
&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Set voltage as low as possible */
&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_POWER_SetVoltage(POWER_BALANCED_MODE, Chip_Clock_GetMainClockRate());
&amp;nbsp;&amp;nbsp;&amp;nbsp; /* Now enter sleep / power down state */
&amp;nbsp;&amp;nbsp;&amp;nbsp; Chip_POWER_EnterPowerMode(powerMode, (SYSCON_PDRUNCFG_PD_WDT_OSC | SYSCON_PDRUNCFG_PD_SRAM0A
&amp;nbsp;&amp;nbsp;&amp;nbsp; | SYSCON_PDRUNCFG_PD_SRAM0B | SYSCON_PDRUNCFG_PD_SRAM1));

while (1) {
}

&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The M0 firmware simply le a led blink.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;the blink is stopped when the M4 goes in low power mode&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I read someone asking whether is possible to let the M0 behave as master, could this be a solution?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;or am I missing something?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:58:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558104#M15547</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:58:02Z</dc:date>
    </item>
    <item>
      <title>Re: M0+ not working when M4 goes in deep sleep mode</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558105#M15548</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by embd02161991 on Fri Jul 10 14:39:44 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The Deep-sleep and power-down modes affect the entire system. In both modes, the clock to all CPUs is shut down and the peripherals receive no internal clocks. So both M0+ and M4 will not have clock in Deep sleep and power down modes.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;NXP Technical Support&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:58:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558105#M15548</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:58:03Z</dc:date>
    </item>
    <item>
      <title>Re: M0+ not working when M4 goes in deep sleep mode</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558106#M15549</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by nerd herd on Fri Jul 10 17:08:52 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: filartrix&lt;/STRONG&gt;&lt;BR /&gt;I read someone asking whether is possible to let the M0 behave as master, could this be a solution?&lt;BR /&gt;or am I missing something?&lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;HR /&gt;&lt;SPAN style="color: #0000ff;"&gt;&lt;STRONG&gt;Quote: embd02161991&lt;/STRONG&gt;&lt;BR /&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;The Deep-sleep and power-down modes affect the entire system. In both modes, the clock to all CPUs is shut down and the peripherals receive no internal clocks. So both M0+ and M4 will not have clock in Deep sleep and power down modes.&lt;BR /&gt;&lt;BR /&gt;Thanks&lt;BR /&gt;NXP Technical Support&lt;/SPAN&gt;&lt;HR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;For clarity, I would like to add onto this answer by saying that making the M0+ core a master will not change anything. &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:58:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/M0-not-working-when-M4-goes-in-deep-sleep-mode/m-p/558106#M15549</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:58:03Z</dc:date>
    </item>
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