topic Re: The relation between EOT, SSD, and SSEL on LPC54102 ????? in LPC Microcontrollers

The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:25 GMT

Content originally posted in LPCWare by okwh on Sat Dec 19 01:21:39 MST 2015
I need to send 24 bits out.
first 8 bits in the first write to TXDATCTL without EOT. and then send 4 bits with EOT

In other word, not allow Deassert (SSEL change) between 8 and 16 bits.

I use STALLED state to judge first 8 bits has sent, and then send 16 bits. (is this right?)

but when I use logic analyzer to check SPI signals, find SSEL change (CS signal) between 8 and 16 bits.!!

What's wrong with it?

I debuged step by step, sure cleared EOT bit in TXCTL before 8 bits, set it befor 16 bits,
and no SDD state after 8 bits.

so why are there SSEL change sinal between 8 and 16 bits seen on logic analyzer ????

as I know , only when I set EOT, then SSD and SSEL change generate after send.
when I clear EOT, then no SSD and no SSEL change generate after send.

but now when I clear EOT, no SSD (with code debug) but have SEEL change (with logic analyzer),

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:25 GMT

Content originally posted in LPCWare by mysepp on Sat Dec 19 01:39:26 MST 2015
Have you thought about configuring SSEL as GPIO and controlling it yourself?

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:26 GMT

Content originally posted in LPCWare by okwh on Sat Dec 19 21:13:28 MST 2015
yes, you are right. all OK if I use software mode.

but LPC54102 has 4+4 SPI for two SPI port, I will use 4+3 with different SCK rate and all master mode
so lot of SPI needed, if I use software simulate mode, not only need a lot of IO codes ,but also need a lot of time to debug and adjust their IO rate and time period.

LPC54102's SPI TXdata is 1~16 bits per pack(frame, or group). more bits data need to be splited in to more parts. But now I find de-assert the SSEL which is not allowed !

below is the states shown in manual:

23.7.6 Data lengths greater than 16 bits
The SPI interface handles data frame sizes from 1 to 16 bits directly. Larger sizes can be handled by splitting data up into groups of 16 bits or less. For example, 24 bits can be supported as 2 groups of 16 bits and 8 bits or 2 groups of 12 bits, among others. Frames of any size, including greater than 32 bits, can supported in the same way.
Details of how to handle larger data widths depend somewhat on other SPI configuration options. For instance, if it is intended for Slave Selects to be deasserted between frames, then this must be suppressed when a larger frame is split into more than one part. Sending 2 groups of 12 bits with SSEL deasserted between 24-bit increments, for instance, would require changing the value of the EOF bit on alternate 12-bit frames.

I needed is Sending 2 groups of 8 and 16 bits with SSEL DEASSERTED between 24-bit increments

but now I find SSEL DEASSERTED between 8 and 16.

Is it possible whether SSEL DEASSERTED related with time-wait between 8 and 16?

Without EOT, should be no SSD, how to judge 1st pack has been sent out ?

maybe I have to use software simulate mode

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:27 GMT

Content originally posted in LPCWare by mysepp on Sun Dec 20 00:15:12 MST 2015
Just to clarify: My hint for GPIO is only for the CS (SSEL), not for CLK/MISO/MOSI.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:27 GMT

Content originally posted in LPCWare by okwh on Sun Dec 20 03:24:10 MST 2015
yes, I know SSEL is CS.

you mean not config SSEL, and only use it as GPIO.
other like SCK/MOSI/MISO are configured as SPI.

I will try,
do not know what happen when I only config SCK/MOSI/MISO pins.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:28 GMT

Content originally posted in LPCWare by mysepp on Sun Dec 20 03:29:35 MST 2015
1) Init SSEL(CS) as GPIO.
2) At the beginning of your transaction, put CS to low (or as you need it).
3) Then start data transfer over SPI/SSP, as long as you want, how much bits are needed by your transaction.
4) When everything is done (transaction is complete, all bits of this transaction is exchanged), put CS to high.
When you have a new transaction, restart at (2).
It is the same way, when you have multiple devices with different CS on one SPI/SSP.
Just select the device (with CSx) you want to send data to/receive data from and do transfer.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:29 GMT

Content originally posted in LPCWare by mysepp on Sun Dec 20 03:31:13 MST 2015
You even don't need to use SSEL as your CS (at least as SPI/SSP master). Take any GPIO you want.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:29 GMT

Content originally posted in LPCWare by okwh on Sun Dec 20 05:02:33 MST 2015
It is a good idea!
I need use its CLK/MOSI/MISO, since I need 7 SPI with different rate, so need use SPI's TXdata register as a buffer. but I do not know when the buffer's content have been sent out. how to judge?

start data transfer over SPI/SSP, as long as you want,

set SPI's TXdata register is fast, it is 1~16 bits.
for larger size data, split it to 2 or more bytes, one byte for one transfer, CS was hold on low,
but how to judge the previous byte has transfered ?

original, I use SSD state as flag to start transfer next byte, now no SSD state without EOT.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:30 GMT

Content originally posted in LPCWare by mysepp on Sun Dec 20 05:12:13 MST 2015
When you send one byte (or x bits) out, then you get one byte (or x bits) in (in parallel, at the same time).
But I think to remember there were flags, when something was completely sent out,
or if there is free space in FIFO. E.g. in LPC4357 you have a FIFO of size 16 bytes, max 8 entries.
So you can send 8 bytes in a go.
Check user manual, chapter about SPI/SSP, status register bits for details.

Re: The relation between EOT, SSD, and SSEL on LPC54102 ?????

lpcware — Wed, 15 Jun 2016 19:58:30 GMT

Content originally posted in LPCWare by okwh on Sun Dec 20 06:25:35 MST 2015
Y..es. received one byte and RXRDY state only when clear RXignore config bit.
no received one byte and no RXRDY state when set RXignore condition.

now I use TXdata register directly. not use FIFO.

maybe FIFO mode is good, but I do not know.

my trouble is I need 7 different SPI with different rate/mode/datalength..., so I don't know whether FIFO mode is suitale.

I will try, Thanks a lot.