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    <title>topic Re: Creating full isolation between the cores  in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556835#M15263</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by TheFallGuy on Thu Nov 28 09:28:28 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The memory spaces of the M4 and M0 on this part is fully shared - so both have full access to each others memory space. There is only one set of peripherals and they are accessible from either/both cores.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;It may be possible to configure the MPU on the M4 to prevent it accessing memory/peripherals outside those that you don't want it to access. Unfortunately, the M0 does not have an MPU, so it is not possible to stop it...&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:40:28 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:40:28Z</dc:date>
    <item>
      <title>Creating full isolation between the cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556834#M15262</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by ippisl on Thu Nov 28 09:01:58 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regarding lpc4300: &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I want to create full isolation between 2 cores: one core will do communications , the other all the rest of the stuff including io. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I want the core that does communication have it's own memory and peripherals, But can't access in anyway the memory and peripherals of the other core. The only interface would be through the shared memory. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is it possible to achieve this ? How ? &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks. &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:40:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556834#M15262</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:40:27Z</dc:date>
    </item>
    <item>
      <title>Re: Creating full isolation between the cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556835#M15263</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by TheFallGuy on Thu Nov 28 09:28:28 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The memory spaces of the M4 and M0 on this part is fully shared - so both have full access to each others memory space. There is only one set of peripherals and they are accessible from either/both cores.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;It may be possible to configure the MPU on the M4 to prevent it accessing memory/peripherals outside those that you don't want it to access. Unfortunately, the M0 does not have an MPU, so it is not possible to stop it...&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:40:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556835#M15263</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:40:28Z</dc:date>
    </item>
    <item>
      <title>Re: Creating full isolation between the cores</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556836#M15264</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by ippisl on Thu Nov 28 11:32:41 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks!&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:40:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Creating-full-isolation-between-the-cores/m-p/556836#M15264</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:40:29Z</dc:date>
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