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    <title>LPC MicrocontrollersのトピックRe: Transmit complete interrupt</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Transmit-complete-interrupt/m-p/556460#M15176</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Tue Feb 17 14:18:23 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;hi, giuslog,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Do you have any timing issues if this is handled with THRE interrupt with a checking of TEMT bit in the LSR register?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;regards,&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:39:31 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:39:31Z</dc:date>
    <item>
      <title>Transmit complete interrupt</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Transmit-complete-interrupt/m-p/556459#M15175</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by giusloq on Wed Feb 11 09:35:59 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I need to have an interrupt as soon as the last bit (stop bit) of the last character in TX FIFO was really transmitted (shifted out). In other words, I'd like to have an interrupt on TEMT flag in LSR register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I need a similar interrupt to TXC (transmit complete) in AVR MCUs from Atmel.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;After reading user manual, I didn't understand if this interrupt is present or not in LPC43xx USART.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:39:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Transmit-complete-interrupt/m-p/556459#M15175</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:39:30Z</dc:date>
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    <item>
      <title>Re: Transmit complete interrupt</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Transmit-complete-interrupt/m-p/556460#M15176</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Tue Feb 17 14:18:23 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;hi, giuslog,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Do you have any timing issues if this is handled with THRE interrupt with a checking of TEMT bit in the LSR register?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;regards,&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:39:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Transmit-complete-interrupt/m-p/556460#M15176</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:39:31Z</dc:date>
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