<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Sharing SysTick hardware/interrupt between cores. in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555960#M15050</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andypevy on Thu Apr 23 03:12:57 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I am (or will eventually be) using freeRTOS on the M0 core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This uses the SysTick timer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How do I use the same timer on the M4 side ?.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Andy&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:55:46 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:55:46Z</dc:date>
    <item>
      <title>Sharing SysTick hardware/interrupt between cores.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555960#M15050</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andypevy on Thu Apr 23 03:12:57 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; I am (or will eventually be) using freeRTOS on the M0 core.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This uses the SysTick timer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;How do I use the same timer on the M4 side ?.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Andy&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:55:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555960#M15050</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:55:46Z</dc:date>
    </item>
    <item>
      <title>Re: Sharing SysTick hardware/interrupt between cores.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555961#M15051</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by starblue on Thu Apr 23 04:54:10 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;The system tick timer is an part of the core, and in the case of the LPC541xx both cores have it (its optional on the M0, and for example the M0 on LPC43xx doesn't have it).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So in your case it is no problem to use it both on the M0 and the M4, as these are two separate timers.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:55:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555961#M15051</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:55:47Z</dc:date>
    </item>
    <item>
      <title>Re: Sharing SysTick hardware/interrupt between cores.</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555962#M15052</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andypevy on Thu Apr 23 05:04:04 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Aha, OK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Andy&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:55:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Sharing-SysTick-hardware-interrupt-between-cores/m-p/555962#M15052</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:55:48Z</dc:date>
    </item>
  </channel>
</rss>

