LPC Microcontrollers中的主题 Re: SPIFI

SPIFI

lpcware — Wed, 15 Jun 2016 18:40:57 GMT

Content originally posted in LPCWare by poonam on Fri Nov 23 06:37:06 MST 2012
I have the SPIFI library.
I want the information about how to read and write into the external flash. Some examples are there to write into flash but they are not explaining how to read from the flash.
I will be thankful if someone can help to solve this issue.

Thanks in advance.

Poonam

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:40:58 GMT

Content originally posted in LPCWare by noahk on Fri Nov 23 11:27:50 MST 2012
The SPIFI library always leaves the SPI Flash readable through the memory mapped range. Read from the 0x14000000 (64 MB mapped) or 0x80000000 (128 MB mapped) to access the SPI Flash data.

Let me know if you have any more questions.

Noah

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:40:59 GMT

Content originally posted in LPCWare by poonam on Mon Dec 03 03:42:25 MST 2012
Hi,

I understood that the area mentioned from 0x1C00 0000 to 0x2000 0000 with different chip selects(CS0,CS1,CS2 and CS3) in LPC4350 is an mirror image of SPIFI data (addresses from 0x140000 0000 to 0x1800 0000). please correct me if i am wrong.

At present we are down loading our application in the area selected by cs0. Can I write some data (with the application existing in the cs0) into the area selected by cs1 and read from SPIFI area?

Is SPIFI data area is read only?

Thanks,
Poonam

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:40:59 GMT

Content originally posted in LPCWare by noahk on Mon Dec 03 16:03:53 MST 2012
Hi Poonam,

That doesn't look to be correct. It looks like 0x1C000000 to 0x20000000 is for static EMC parallel memory. The SPIFI is a serial memory.

The SPIFI data area is read-only.

Noah

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:00 GMT

Content originally posted in LPCWare by poonam on Tue Dec 04 05:10:30 MST 2012
Thanks for the confirmation ....

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:00 GMT

Content originally posted in LPCWare by poonam on Tue Dec 04 05:14:03 MST 2012
Hi,

In the memory map of LPC4350, local SRAM is expanded and it includes SPIFI data(0x18000000 - 0x14000000).
may i know what is SPIFI data at 0x8000000..

Thanks
Poonam

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:01 GMT

Content originally posted in LPCWare by noahk on Thu Dec 06 17:05:29 MST 2012
Hi Poonam,

SPIFI data is mapped at both 0x14000000 and 0x80000000. The lower range is smaller, but also lives on the I(nstruction) and D(ata) buses of the Cortex allowing for a slight performance improvement when running from the 0x14000000 range.

The first 64 MB of the SPI Flash is readable in the same way from the start of both of these ranges. The upper range also maps an additional 64 MB of the SPI Flash.

Noah

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:02 GMT

Content originally posted in LPCWare by nxp21346 on Tue Dec 11 14:31:00 MST 2012
Hi All,

A new version of the SPIFI library has been released. It should result in a minor performance improvement with no changes to the calling code.

-Dave @ NXP

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:02 GMT

Content originally posted in LPCWare by poonam on Fri Feb 08 04:59:35 MST 2013
Hi Dave,

Can i get the files of this library as i have to call the read API to read MP3 files from Flash.?

Thanks & regards,
Poonam

Re: SPIFI

lpcware — Wed, 15 Jun 2016 18:41:03 GMT

Content originally posted in LPCWare by Adambravo on Fri Jan 29 03:16:17 MST 2016
This is less useful for just moving boot code to SRAM. Can already do that with a peripheral SPI port. The benefit is for running code. Even if it is just boot code, or patching ROM code, it alleviates having a large chunk of SRAM on chip to hold this running code when speed is not an issue. SRAM is large on chip. With Qual SPI speed top coolgadgets review online, one would hope for increased processing use also (faster access).