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    <title>topic I2S with DMA transferring 32bit stereo audio issue in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/I2S-with-DMA-transferring-32bit-stereo-audio-issue/m-p/555616#M14981</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by tanabe on Sun Oct 18 22:15:34 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPC4357 chip, I want to play audio at GPIO interrupt, so setting DMA transfer from memory to I2S peripheral in GPIO interrupt function. then L/R channel output is inverted occasionally.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;My procedure is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Setting I2S output format (32bit Stereo)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Turn I2S_DAO RESET bit to 0 (STOP bit is 1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In GPIO interrupt,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Set DMA, and start transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Wait TX_LEVEL is to higher than TX_DEPTH_DMA1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 3. Turn I2S_DAO STOP to 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In this procedure, it will occur once per 1000 times that L/R channel inverting in output.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Inverting occurs only at beginning of transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Why occurs Inverting?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;And, I found work-around for this problem with substitute procedure in GPIO interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;New procedure in GPIO interrupt is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Write 0 to I2S_TX_FIFO.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Turn I2S_DAO STOP to 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 3. Wait TX_LEVEL is 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 4. Set DMA, and start transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Then, L/R inverting never occur. But, I don't understand why the procedure can avoid the problem.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Does the work-around do well?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This issue seemed to be related the article in following link, but divied topic, because I use other chip and output audio.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fforum%2Fstereo-i2s-and-dma-issue" rel="nofollow" target="_blank"&gt;https://www.lpcware.com/content/forum/stereo-i2s-and-dma-issue&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tanabe&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:41:35 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:41:35Z</dc:date>
    <item>
      <title>I2S with DMA transferring 32bit stereo audio issue</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/I2S-with-DMA-transferring-32bit-stereo-audio-issue/m-p/555616#M14981</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by tanabe on Sun Oct 18 22:15:34 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPC4357 chip, I want to play audio at GPIO interrupt, so setting DMA transfer from memory to I2S peripheral in GPIO interrupt function. then L/R channel output is inverted occasionally.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;My procedure is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Setting I2S output format (32bit Stereo)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Turn I2S_DAO RESET bit to 0 (STOP bit is 1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In GPIO interrupt,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Set DMA, and start transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Wait TX_LEVEL is to higher than TX_DEPTH_DMA1&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 3. Turn I2S_DAO STOP to 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In this procedure, it will occur once per 1000 times that L/R channel inverting in output.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Inverting occurs only at beginning of transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Why occurs Inverting?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;And, I found work-around for this problem with substitute procedure in GPIO interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;New procedure in GPIO interrupt is:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 1. Write 0 to I2S_TX_FIFO.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 2. Turn I2S_DAO STOP to 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 3. Wait TX_LEVEL is 0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; 4. Set DMA, and start transfer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Then, L/R inverting never occur. But, I don't understand why the procedure can avoid the problem.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Does the work-around do well?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;This issue seemed to be related the article in following link, but divied topic, because I use other chip and output audio.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fforum%2Fstereo-i2s-and-dma-issue" rel="nofollow" target="_blank"&gt;https://www.lpcware.com/content/forum/stereo-i2s-and-dma-issue&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tanabe&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:41:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/I2S-with-DMA-transferring-32bit-stereo-audio-issue/m-p/555616#M14981</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:41:35Z</dc:date>
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