topic Re: Cortex-M4 and Cortex-M0 code from same bank, is it possible? How much slower is it? in LPC Microcontrollers

Cortex-M4 and Cortex-M0 code from same bank, is it possible? How much slower is it?

lpcware — Wed, 15 Jun 2016 18:39:03 GMT

Content originally posted in LPCWare by mysepp on Fri Mar 18 04:36:03 MST 2016
Would it in general be possible to place Cortex-M4 and Cortex-M0 code both in same flash bank
e.g. Cortex-M4 code in first half of bank A, Cortex-M0 code in second half of bank A?

Would it be extremely slower than
e.g. compared to Cortex-M4 code in bank A and Cortex-M0 code in bank B?

Is having Cortex-M4 code in bank A and Cortex-M0 code in bank B equal or slower
then putting Cortex-M0 code into SRAM?

Re: Cortex-M4 and Cortex-M0 code from same bank, is it possible? How much slower is it?

lpcware — Wed, 15 Jun 2016 18:39:04 GMT

Content originally posted in LPCWare by starblue on Fri Mar 18 05:40:02 MST 2016

Quote: mysepp
Would it in general be possible to place Cortex-M4 and Cortex-M0 code both in same flash bank
e.g. Cortex-M4 code in first half of bank A, Cortex-M0 code in second half of bank A?

Yes.

Quote:
Would it be extremely slower than
e.g. compared to Cortex-M4 code in bank A and Cortex-M0 code in bank B?

Yes. I would expect a factor of about three (see below).

Quote:
Is having Cortex-M4 code in bank A and Cortex-M0 code in bank B equal or slower
then putting Cortex-M0 code into SRAM?

In my experience SRAM is the fastest as there are no wait states, an M4 running from flash is about 3 times slower at 200 MHz and 9 wait states. From the wait states alone it should be 10 times slower, but the caching in the flash accelerator compensates that somewhat. If you run two cores on the same flash I would expect that the caching / prefetching becomes ineffective, so I would expect a slowdown by the full factor of 10.
The effectiveness of caching depends on the code. If your code spends a lot of time in small loops or straight-line code it could run faster, if it does a lot of branching it could run slower.

Re: Cortex-M4 and Cortex-M0 code from same bank, is it possible? How much slower is it?

lpcware — Wed, 15 Jun 2016 18:39:05 GMT

Content originally posted in LPCWare by bavarian on Thu Apr 07 04:09:50 MST 2016
Two cores running code from the same memory bank is in general possible, but not a good idea.
It's pretty unpredictable where you end up with the performance of the two cores.
There will be a lot of bus stalling and the flash accelerator of the internal flash gets more or less disabled with this setup.

Regards,
NXP Support Team.

Re: Cortex-M4 and Cortex-M0 code from same bank, is it possible? How much slower is it?

lpcware — Sun, 19 Jun 2016 01:05:42 GMT

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