LPC MicrocontrollersのトピックRunning from flash code on both cores.

Running from flash code on both cores.

lpcware — Wed, 15 Jun 2016 19:57:19 GMT

Content originally posted in LPCWare by andypevy on Mon Apr 13 06:34:03 MST 2015
Hi,

Are there any details available for setting up a dual code project
where both cores run simultaneously from Flash, rather than having
one running from a ram copy of the flash ?.

Thanks,
Andy

Re: Running from flash code on both cores.

lpcware — Wed, 15 Jun 2016 19:57:20 GMT

Content originally posted in LPCWare by lpcxpresso-support on Mon Apr 13 08:27:47 MST 2015
The projects are setup this way for a very good reason - there is only a single bank of flash and if you try to run both cores from the same flash you will get flash contention which will cripple your performance on BOTH cores. So, our advice is - do not do this.

Re: Running from flash code on both cores.

lpcware — Wed, 15 Jun 2016 19:57:21 GMT

Content originally posted in LPCWare by nerd herd on Tue Apr 14 08:12:00 MST 2015
Hi andypevy,

You may want to take a look at AN11609:

http://www.lpcware.com/content/nxpfile/lpc54100-dual-core-usage-application-note

Re: Running from flash code on both cores.

lpcware — Wed, 15 Jun 2016 19:57:21 GMT

Content originally posted in LPCWare by andypevy on Wed Apr 15 00:38:21 MST 2015
Hi,

I saw this, and had assumed that the part :-

• Access to the flash can happen in parallel, the Cortex-M4F uses the I-code and the D-code bus for
code execution whereas the Cortex-M0+ uses the System bus. Access to SRAM can also be split onto
SRAM0 and SRAM1.

Meant that I could run both cores from flash (Albeit different parts) simultaneously.

Andy

Re: Running from flash code on both cores.

lpcware — Wed, 15 Jun 2016 19:57:22 GMT

Content originally posted in LPCWare by lpcxpresso-support on Wed Apr 15 02:17:57 MST 2015

Quote:
• Access to the flash can happen in parallel, the Cortex-M4F uses the I-code and the D-code bus for
code execution whereas the Cortex-M0+ uses the System bus. Access to SRAM can also be split onto
SRAM0 and SRAM1.

This comment is strictly true - both cores have access to the entire memory system. However, if both cores are accessing the same memory bank (flash or RAM) at the same time, then you will have contention. If accessing of the same memory is rare (i.e. passing messages) then the performance hit will be negligable, but if it is constant (i.e. fetching instructions) then performance will seriously degrade.

Hope that is clear. I will ask somebody to consider making this more explicit in the Application Notes and User Manual.