<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic lpc13xx in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc13xx/m-p/554150#M14690</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by wellsk on Fri May 20 13:15:57 MST 2011&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;h2 class="h2off" title="Back to top"&amp;gt;Introduction&amp;lt;/h2&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;table class="widthindent"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;tbody&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;tr&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;&amp;lt;td class="middle" width="180"&amp;gt;&amp;lt;span class="inline inline-left"&amp;gt;&amp;lt;img class="image image-preview " src="&lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fsystem%2Ffiles%2Fimages%2FLPC1347%2520block%2520diagram.preview.png" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/system/files/images/LPC1347%20block%20diagram.preview.png&lt;/A&gt;&lt;SPAN&gt;" border="0" alt="" title="" width="505" height="640" /&amp;gt;&amp;lt;/span&amp;gt;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;td width="10"&amp;gt;&amp;nbsp;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;td class="middle"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;h3&amp;gt;&amp;nbsp;&amp;lt;/h3&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/tr&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/tbody&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/table&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The LPC13xx devices are ARM Cortex-M3-based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The LPC13xx devices operate at CPU frequencies of up to 72MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The peripheral complement of the LPC13xx includes up to 32KB of flash memory, up to 8KB of data memory, USB Device (LPC134x only), one Fast-mode plus (Fm+) I&amp;lt;sup&amp;gt;2&amp;lt;/sup&amp;gt;C interface, one UART, four general purpose timers, and up to 42 general purpose I/O pins. &amp;nbsp;&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:54:01 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:54:01Z</dc:date>
    <item>
      <title>lpc13xx</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/lpc13xx/m-p/554150#M14690</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by wellsk on Fri May 20 13:15:57 MST 2011&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;h2 class="h2off" title="Back to top"&amp;gt;Introduction&amp;lt;/h2&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;table class="widthindent"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;tbody&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;tr&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;&amp;lt;td class="middle" width="180"&amp;gt;&amp;lt;span class="inline inline-left"&amp;gt;&amp;lt;img class="image image-preview " src="&lt;/SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fsystem%2Ffiles%2Fimages%2FLPC1347%2520block%2520diagram.preview.png" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/system/files/images/LPC1347%20block%20diagram.preview.png&lt;/A&gt;&lt;SPAN&gt;" border="0" alt="" title="" width="505" height="640" /&amp;gt;&amp;lt;/span&amp;gt;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;td width="10"&amp;gt;&amp;nbsp;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;td class="middle"&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;h3&amp;gt;&amp;nbsp;&amp;lt;/h3&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/td&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/tr&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/tbody&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/table&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The LPC13xx devices are ARM Cortex-M3-based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The LPC13xx devices operate at CPU frequencies of up to 72MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;lt;div class="indent"&amp;gt;The peripheral complement of the LPC13xx includes up to 32KB of flash memory, up to 8KB of data memory, USB Device (LPC134x only), one Fast-mode plus (Fm+) I&amp;lt;sup&amp;gt;2&amp;lt;/sup&amp;gt;C interface, one UART, four general purpose timers, and up to 42 general purpose I/O pins. &amp;nbsp;&amp;lt;/div&amp;gt;&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:54:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/lpc13xx/m-p/554150#M14690</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:54:01Z</dc:date>
    </item>
  </channel>
</rss>

