<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>LPC Microcontrollers中的主题 Static EMC_CS1 does multiple write cycles</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553297#M14538</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by khfreiberg on Thu Jul 17 15:51:56 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a LPC4337 with a FPGA connected to static CS1 for 16 bit wide memory mapped hardware access. I have an external analyzer connected to see what the controller is doing.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;What I see on the bus doesn't correspond to the code. Even when I single step through the code I see 8 write cycles on consequtive addresses for a single 32 bit write in the code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It looks like paging, but the PM bit in STATICCONFIG1 is set to 'OFF'. I am writing 0x81 to the register and enable the buffer that's it. Reading back 0x40005220 show 0x00080081 as expected.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Can anybody tell me which other register is controlling this? &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:37:40 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:37:40Z</dc:date>
    <item>
      <title>Static EMC_CS1 does multiple write cycles</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553297#M14538</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by khfreiberg on Thu Jul 17 15:51:56 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a LPC4337 with a FPGA connected to static CS1 for 16 bit wide memory mapped hardware access. I have an external analyzer connected to see what the controller is doing.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;What I see on the bus doesn't correspond to the code. Even when I single step through the code I see 8 write cycles on consequtive addresses for a single 32 bit write in the code.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It looks like paging, but the PM bit in STATICCONFIG1 is set to 'OFF'. I am writing 0x81 to the register and enable the buffer that's it. Reading back 0x40005220 show 0x00080081 as expected.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Can anybody tell me which other register is controlling this? &lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:37:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553297#M14538</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:37:40Z</dc:date>
    </item>
    <item>
      <title>Re: Static EMC_CS1 does multiple write cycles</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553298#M14539</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by mc on Thu Jul 17 16:06:00 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi khfreiberg,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Please see below thread.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fforum%2Femc-generates-double-read-cycles-static-chip-selects%23comment-1135927" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/forum/emc-generates-double-read-cycles-static-chip-selects#comment-1135927&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:37:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553298#M14539</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:37:41Z</dc:date>
    </item>
    <item>
      <title>Re: Static EMC_CS1 does multiple write cycles</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553299#M14540</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by wmues on Fri Jul 18 07:40:56 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Have you tried to disable the buffer?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:37:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Static-EMC-CS1-does-multiple-write-cycles/m-p/553299#M14540</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:37:41Z</dc:date>
    </item>
  </channel>
</rss>

