LPC MicrocontrollersのトピックAdvice for predictable DMA timing? https://community.nxp.com/t5/LPC-Microcontrollers/Advice-for-predictable-DMA-timing/m-p/551717#M14240 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by rockyh on Fri Sep 19 08:12:44 MST 2014</STRONG><BR /><SPAN>Hi,</SPAN><BR /><SPAN>I have a design where I am using a State Configurable Timer event to generate a single 16 bit DMA transfer from external SRAM to the internal RAM of the 4330.&nbsp; The external SRAM EMC is set to zero wait states, and running the core at 204MHz.</SPAN><BR /><SPAN>At slower speeds this works without issue, but as I bring the SCT up to the speed where we need it (the DMA transfer needs to occur within 200 nsec), I start to see unexpected "glitches" where the DMA transfer is delayed. This doesn't happen very often, but often enough that it is a problem.</SPAN><BR /><SPAN>The code is running in the internal SRAM of the 4330 and interrupts are disabled.</SPAN><BR /><SPAN>I'm looking for any advice or tips.&nbsp; Is this "glitch" something to expect with DMA? Is there anyway to avoid this?</SPAN><BR /><SPAN>Thank you</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:36:29 GMT lpcware 2016-06-15T18:36:29Z Advice for predictable DMA timing? https://community.nxp.com/t5/LPC-Microcontrollers/Advice-for-predictable-DMA-timing/m-p/551717#M14240 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by rockyh on Fri Sep 19 08:12:44 MST 2014</STRONG><BR /><SPAN>Hi,</SPAN><BR /><SPAN>I have a design where I am using a State Configurable Timer event to generate a single 16 bit DMA transfer from external SRAM to the internal RAM of the 4330.&nbsp; The external SRAM EMC is set to zero wait states, and running the core at 204MHz.</SPAN><BR /><SPAN>At slower speeds this works without issue, but as I bring the SCT up to the speed where we need it (the DMA transfer needs to occur within 200 nsec), I start to see unexpected "glitches" where the DMA transfer is delayed. This doesn't happen very often, but often enough that it is a problem.</SPAN><BR /><SPAN>The code is running in the internal SRAM of the 4330 and interrupts are disabled.</SPAN><BR /><SPAN>I'm looking for any advice or tips.&nbsp; Is this "glitch" something to expect with DMA? Is there anyway to avoid this?</SPAN><BR /><SPAN>Thank you</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:36:29 GMT https://community.nxp.com/t5/LPC-Microcontrollers/Advice-for-predictable-DMA-timing/m-p/551717#M14240 lpcware 2016-06-15T18:36:29Z Re: Advice for predictable DMA timing? https://community.nxp.com/t5/LPC-Microcontrollers/Advice-for-predictable-DMA-timing/m-p/551718#M14241 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by starblue on Sat Sep 20 01:16:26 MST 2014</STRONG><BR /><SPAN>Is there contention for the external or internal RAM, i.e. is a processor accessing it simultaneously with the DMA?</SPAN><BR /><SPAN>Are the code and the data in different RAM areas? Take a look at UM10503 "3.6 AHB Multilayer matrix configuration".</SPAN><BR /><SPAN>How many read/write cycles can the external RAM do in 200ns? Since external RAM is slower than internal memory, it is more likely to be the culprit.</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:36:30 GMT https://community.nxp.com/t5/LPC-Microcontrollers/Advice-for-predictable-DMA-timing/m-p/551718#M14241 lpcware 2016-06-15T18:36:30Z