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    <title>LPC MicrocontrollersのトピックCannot set DMA transfersize</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-set-DMA-transfersize/m-p/548997#M13757</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by khorght on Mon Dec 02 11:53:50 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;MCU - LPC2364&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;IDE - IAR 6.50.3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;All seems fine,but... in debugger i see corretly set burst, src/dst, etc bits but transfersize field is always stays zero even if just write 0x01 to Control register for test purposes.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tryed to enable DMA first, tryed to enable channel first, tryed to force channel configuration&amp;nbsp; register to zero for mem-to-mem transfer but transfersize can't be set.the strangest thing is that transfer occures one time, i see execution of the handler where TC status flag resets and TCCount variable increments by 1.&amp;nbsp; Here's the part of the code ( uses my own library - fully working with all other periphery, except DMA)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_DeInit(DMACC1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitTypeDef DMA_InitStruct;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_TransferSize = (uint16_t)((0x1000 / 4) &amp;amp; 0x0FFF); /* 0x1000 is DMA_SIZE */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcBaseAddr = 0x7FD00000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestBaseAddr = 0x7FD01000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_Flow = DMA_Flow_MemToMem_DMA;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcBurst = DMA_BurstSize32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestBurst = DMA_BurstSize32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcDataSize = DMA_TransferWidth32bits;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestDataSize = DMA_TransferWidth32bits;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcInc = DMA_InrementAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestInc = DMA_InrementAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_Protection = DMA_Protection_Default;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_TerminalCountInt = DMA_TerminalCountIntEnable;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t i;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t *src_addr, *dest_addr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;src_addr = (uint32_t *)0x7FD00000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;dest_addr = (uint32_t *)0x7FD01000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;for ( i = 0; i &amp;lt; 0x1000 / 4; i ++ )&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;*src_addr = i;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;*dest_addr = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;src_addr++;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;dest_addr++;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Enable DMA */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Init(DMACC1, &amp;amp;DMA_InitStruct);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Endiannes(DMA_LittleEndian);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Cmd(ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_ChannelCmd(DMACC1, ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void DMA_Init(DMACC_TypeDef *DMACCx, DMA_InitTypeDef* DMA_InitStruct)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Clear Any pending interrupts */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;if (DMACCx == DMACC0)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTTCCLEAR = DMA_Channel0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTERRCLR = DMA_Channel0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;else if (DMACCx == DMACC1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTTCCLEAR = DMA_Channel1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTERRCLR = DMA_Channel1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Configure DMA Channel */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;SRCADDR = DMA_InitStruct-&amp;gt;DMA_SrcBaseAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;DESTADDR = DMA_InitStruct-&amp;gt;DMA_DestBaseAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Write the address of the next Linked List Item (LLI), or 0 if transfer - single packet */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACC0-&amp;gt;LLI = 0;//DMA_LLI;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Flow Control */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONTROL |= (((0x40 &amp;amp; 0xFFF) &amp;lt;&amp;lt; 0));&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONFIGURATION |= DMA_InitStruct-&amp;gt;DMA_Flow;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONTROL = (((DMA_InitStruct-&amp;gt;DMA_TransferSize &amp;amp; 0xFFF) &amp;lt;&amp;lt; 0))&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcBurst &amp;lt;&amp;lt; 12)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestBurst &amp;lt;&amp;lt; 15)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcDataSize &amp;lt;&amp;lt; 18)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestDataSize &amp;lt;&amp;lt; 21)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcInc &amp;lt;&amp;lt; 26) //Source increment(src addr will be incremented after each transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestInc &amp;lt;&amp;lt; 27) //Destination increment(dst addr will be incremented after each transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| DMA_InitStruct-&amp;gt;DMA_Protection /* Set DMA Channel Protection */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| DMA_InitStruct-&amp;gt;DMA_TerminalCountInt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;what am i doing wrong?thanx.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:50:04 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:50:04Z</dc:date>
    <item>
      <title>Cannot set DMA transfersize</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-set-DMA-transfersize/m-p/548997#M13757</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by khorght on Mon Dec 02 11:53:50 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;MCU - LPC2364&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;IDE - IAR 6.50.3&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;All seems fine,but... in debugger i see corretly set burst, src/dst, etc bits but transfersize field is always stays zero even if just write 0x01 to Control register for test purposes.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Tryed to enable DMA first, tryed to enable channel first, tryed to force channel configuration&amp;nbsp; register to zero for mem-to-mem transfer but transfersize can't be set.the strangest thing is that transfer occures one time, i see execution of the handler where TC status flag resets and TCCount variable increments by 1.&amp;nbsp; Here's the part of the code ( uses my own library - fully working with all other periphery, except DMA)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_DeInit(DMACC1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitTypeDef DMA_InitStruct;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_TransferSize = (uint16_t)((0x1000 / 4) &amp;amp; 0x0FFF); /* 0x1000 is DMA_SIZE */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcBaseAddr = 0x7FD00000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestBaseAddr = 0x7FD01000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_Flow = DMA_Flow_MemToMem_DMA;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcBurst = DMA_BurstSize32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestBurst = DMA_BurstSize32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcDataSize = DMA_TransferWidth32bits;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestDataSize = DMA_TransferWidth32bits;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_SrcInc = DMA_InrementAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_DestInc = DMA_InrementAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_Protection = DMA_Protection_Default;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_InitStruct.DMA_TerminalCountInt = DMA_TerminalCountIntEnable;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t i;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;uint32_t *src_addr, *dest_addr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;src_addr = (uint32_t *)0x7FD00000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;dest_addr = (uint32_t *)0x7FD01000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;for ( i = 0; i &amp;lt; 0x1000 / 4; i ++ )&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;*src_addr = i;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;*dest_addr = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;src_addr++;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;dest_addr++;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Enable DMA */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Init(DMACC1, &amp;amp;DMA_InitStruct);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Endiannes(DMA_LittleEndian);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_Cmd(ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMA_ChannelCmd(DMACC1, ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;void DMA_Init(DMACC_TypeDef *DMACCx, DMA_InitTypeDef* DMA_InitStruct)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Clear Any pending interrupts */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;if (DMACCx == DMACC0)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTTCCLEAR = DMA_Channel0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTERRCLR = DMA_Channel0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;else if (DMACCx == DMACC1)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;{&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTTCCLEAR = DMA_Channel1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMAC-&amp;gt;INTERRCLR = DMA_Channel1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Configure DMA Channel */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;SRCADDR = DMA_InitStruct-&amp;gt;DMA_SrcBaseAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;DESTADDR = DMA_InitStruct-&amp;gt;DMA_DestBaseAddr;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Write the address of the next Linked List Item (LLI), or 0 if transfer - single packet */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACC0-&amp;gt;LLI = 0;//DMA_LLI;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Flow Control */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONTROL |= (((0x40 &amp;amp; 0xFFF) &amp;lt;&amp;lt; 0));&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONFIGURATION |= DMA_InitStruct-&amp;gt;DMA_Flow;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;DMACCx-&amp;gt;CONTROL = (((DMA_InitStruct-&amp;gt;DMA_TransferSize &amp;amp; 0xFFF) &amp;lt;&amp;lt; 0))&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcBurst &amp;lt;&amp;lt; 12)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestBurst &amp;lt;&amp;lt; 15)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcDataSize &amp;lt;&amp;lt; 18)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestDataSize &amp;lt;&amp;lt; 21)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_SrcInc &amp;lt;&amp;lt; 26) //Source increment(src addr will be incremented after each transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| (DMA_InitStruct-&amp;gt;DMA_DestInc &amp;lt;&amp;lt; 27) //Destination increment(dst addr will be incremented after each transfer)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| DMA_InitStruct-&amp;gt;DMA_Protection /* Set DMA Channel Protection */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;| DMA_InitStruct-&amp;gt;DMA_TerminalCountInt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;what am i doing wrong?thanx.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:50:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-set-DMA-transfersize/m-p/548997#M13757</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:50:04Z</dc:date>
    </item>
    <item>
      <title>Re: Cannot set DMA transfersize</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-set-DMA-transfersize/m-p/548998#M13758</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by triffid_hunter on Sun Dec 15 19:49:45 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;TransferSize is a magic dual-purpose register, like SSP-&amp;gt;DR - that is, it performs a different function when written or read.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When written, it stores the TransferSize value in the DMA engine *somewhere*.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When read, it returns the number of transfers remaining for the active or halted channel.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;As a result, it will always read zero after being written, but before the channel has begun transferring.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;You should be extremely careful of read-modify-write operations on this register. TransferSize should be updated last.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I just went through this confusion myself :)&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:50:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Cannot-set-DMA-transfersize/m-p/548998#M13758</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:50:05Z</dc:date>
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