<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic GPIO Weak Pull-down in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/GPIO-Weak-Pull-down/m-p/548824#M13716</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by demckinley1 on Thu Jan 15 16:48:35 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Part: LPC2214, On GPIO Port0, the pins appear to have an internal weak pull-down when programmed as an input after reset. Is this the case?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:48:59 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:48:59Z</dc:date>
    <item>
      <title>GPIO Weak Pull-down</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/GPIO-Weak-Pull-down/m-p/548824#M13716</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by demckinley1 on Thu Jan 15 16:48:35 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Part: LPC2214, On GPIO Port0, the pins appear to have an internal weak pull-down when programmed as an input after reset. Is this the case?&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:48:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/GPIO-Weak-Pull-down/m-p/548824#M13716</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:48:59Z</dc:date>
    </item>
  </channel>
</rss>

