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    <title>topic My trouble onLPC4088 and MT48LC4M32B2P75 in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/My-trouble-onLPC4088-and-MT48LC4M32B2P75/m-p/546402#M13252</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andrewchen on Wed Apr 16 09:12:58 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi Friend,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; I have some trouble on debug MT48LC4M32B2975,Could anybody give me hand?thanks.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; config.ChipSize = 128;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AddrBusWidth = 32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AddrMap = EMC_ADD_MAP_ROW_BANK_COL ;/*EMC_ADD_MAP_BANK_ROW_COL ;*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.CSn = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataWidth =32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.TotalSize = SDRAM_SIZE*8;//SDRAM_SIZE = 0x 1000000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.CASLatency= 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.RASLatency= 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.Active2ActivePeriod =3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ActiveBankLatency =10;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AutoRefrehPeriod = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataIn2ActiveTime =2;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataOut2ActiveTime = 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.WriteRecoveryTime = 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ExitSelfRefreshTime = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.LoadModeReg2Active = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.PrechargeCmdPeriod = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ReadConfig = 1;&amp;nbsp; // Command delayed strategy, using EMCCLKDELAY &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.RefreshTime = 0x2E;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.Active2PreChargeTime = 2;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.SeftRefreshExitTime = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;dwtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32&amp;lt;&amp;lt;12))); /* Mode Register Setting: 4 burst, 3 CAS latency */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt; LPC_EMC-&amp;gt;DynamicConfig0 = 0x00004500;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;above is&amp;nbsp; config for SDRam and following is troubles.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;1)Bank0 (A0000000~A03fffff) cofuse with Bank1 (A0400000~A07fffff)&amp;nbsp; ,and Bank2(A0800000~A0bfffff)&amp;nbsp; confuse with Bank3(A0c00000~A0ffffff).That means when write into Bank1,it would cover Bank0&amp;nbsp; before writed .The same as bank2 and bank3.it look like the EMC_A13 can not work well.But I check EMC_A13 well by GPIO function.i almost can sure that hardware OK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2)if it write a single bank ,and then verify time and time.all&amp;nbsp; is pass.if firstly write bank0 ,secondly write bank2 and then verify bank0,it will fail at every sector from 0xaXXXn400 to 0xaXXX(n+1)000. From 0xaXXXn000 to 0xaXXXn3fff is verify pass. Even if secondly not write bank2 but verify bank2,it also get the same result.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I not sure if the problem exist in address map or sdram refresh. Could anybody help me? thanks!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:32:47 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:32:47Z</dc:date>
    <item>
      <title>My trouble onLPC4088 and MT48LC4M32B2P75</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/My-trouble-onLPC4088-and-MT48LC4M32B2P75/m-p/546402#M13252</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by andrewchen on Wed Apr 16 09:12:58 MST 2014&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi Friend,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; I have some trouble on debug MT48LC4M32B2975,Could anybody give me hand?thanks.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; config.ChipSize = 128;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AddrBusWidth = 32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AddrMap = EMC_ADD_MAP_ROW_BANK_COL ;/*EMC_ADD_MAP_BANK_ROW_COL ;*/&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.CSn = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataWidth =32;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.TotalSize = SDRAM_SIZE*8;//SDRAM_SIZE = 0x 1000000;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.CASLatency= 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.RASLatency= 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.Active2ActivePeriod =3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ActiveBankLatency =10;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.AutoRefrehPeriod = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataIn2ActiveTime =2;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.DataOut2ActiveTime = 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.WriteRecoveryTime = 1;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ExitSelfRefreshTime = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.LoadModeReg2Active = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.PrechargeCmdPeriod = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.ReadConfig = 1;&amp;nbsp; // Command delayed strategy, using EMCCLKDELAY &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.RefreshTime = 0x2E;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.Active2PreChargeTime = 2;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; config.SeftRefreshExitTime = 3;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;dwtemp = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32&amp;lt;&amp;lt;12))); /* Mode Register Setting: 4 burst, 3 CAS latency */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt; LPC_EMC-&amp;gt;DynamicConfig0 = 0x00004500;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;above is&amp;nbsp; config for SDRam and following is troubles.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;1)Bank0 (A0000000~A03fffff) cofuse with Bank1 (A0400000~A07fffff)&amp;nbsp; ,and Bank2(A0800000~A0bfffff)&amp;nbsp; confuse with Bank3(A0c00000~A0ffffff).That means when write into Bank1,it would cover Bank0&amp;nbsp; before writed .The same as bank2 and bank3.it look like the EMC_A13 can not work well.But I check EMC_A13 well by GPIO function.i almost can sure that hardware OK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2)if it write a single bank ,and then verify time and time.all&amp;nbsp; is pass.if firstly write bank0 ,secondly write bank2 and then verify bank0,it will fail at every sector from 0xaXXXn400 to 0xaXXX(n+1)000. From 0xaXXXn000 to 0xaXXXn3fff is verify pass. Even if secondly not write bank2 but verify bank2,it also get the same result.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I not sure if the problem exist in address map or sdram refresh. Could anybody help me? thanks!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:32:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/My-trouble-onLPC4088-and-MT48LC4M32B2P75/m-p/546402#M13252</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:32:47Z</dc:date>
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