<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic Re: Too many IRQs for ADC (LPC4078) in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Too-many-IRQs-for-ADC-LPC4078/m-p/546073#M13189</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by g_mocken on Thu Feb 04 04:09:20 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Problem identified:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_SetSampleRate() calls getClkDiv(). The latter does not return anything useful, if the desired rate cannot be achieved with the current peripheral clock, as it is the case here:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1kHz desired, meaning a ADC clock of 31kHz.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;With PCLK=60 Mhz and a maximum divider of 256 we get 60 Mhz / 256 = 234kHz &amp;gt;&amp;gt; 31 kHz.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Lowering PCLK to 8 Mhz&amp;nbsp; would probably work (but would seriously affect other peripherals). I have now resorted to using a software timer and the ADC in non-Burst mode (i.e. single shots).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I would still suggest to change Chip_ADC_SetSampleRate() and let it return the actually achieved sample rate (or at least return an error in such a case as mine).&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:29:55 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:29:55Z</dc:date>
    <item>
      <title>Too many IRQs for ADC (LPC4078)</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Too-many-IRQs-for-ADC-LPC4078/m-p/546072#M13188</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by g_mocken on Tue Feb 02 08:51:56 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Following the sample code and docs, I initialize the AD conversion roughly like the following:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;static ADC_CLOCK_SETUP_T ADCSetup;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_Init(LPC_ADC, &amp;amp;ADCSetup);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_EnableChannel(LPC_ADC, _ADC_CHANNEL, ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_SetBurstCmd(LPC_ADC, ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_SetStartMode(LPC_ADC, ADC_NO_START, ADC_TRIGGERMODE_RISING);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_SetSampleRate(LPC_ADC, &amp;amp;ADCSetup, 1000); // &amp;lt;-- sample rate 1000 Hz&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;NVIC_EnableIRQ(ADC_IRQn);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_Int_SetChannelCmd(LPC_ADC, _ADC_CHANNEL, ENABLE);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;My ISR looks like this:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;uint16_t dataADC;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_ReadValue(LPC_ADC, _ADC_CHANNEL, &amp;amp;dataADC);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;NVIC_ClearPendingIRQ(ADC_IRQn);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The result however is (I checked by toggeling a GPIO line and using a scope) that the ISR is called at a rate of around 6379 Hz instead of 1000 Hz (as configured). The ADC samples themselves are correct. &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When I vary the sample rate in Chip_ADC_SetSampleRate(), the IRQ rate also changes, but the relation between the two does not make much sense (e.g. twice the rate: 2000 Hz result in measured 4560 Hz)&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Is there something wrong in the clock setup or is there any additional IRQ register that I need to clear in the ISR (to preventing it from being called several times for the same IRQ)?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Any hints would be appreciated,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;G.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:29:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Too-many-IRQs-for-ADC-LPC4078/m-p/546072#M13188</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:29:54Z</dc:date>
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    <item>
      <title>Re: Too many IRQs for ADC (LPC4078)</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Too-many-IRQs-for-ADC-LPC4078/m-p/546073#M13189</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by g_mocken on Thu Feb 04 04:09:20 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Problem identified:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ADC_SetSampleRate() calls getClkDiv(). The latter does not return anything useful, if the desired rate cannot be achieved with the current peripheral clock, as it is the case here:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;1kHz desired, meaning a ADC clock of 31kHz.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;With PCLK=60 Mhz and a maximum divider of 256 we get 60 Mhz / 256 = 234kHz &amp;gt;&amp;gt; 31 kHz.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Lowering PCLK to 8 Mhz&amp;nbsp; would probably work (but would seriously affect other peripherals). I have now resorted to using a software timer and the ADC in non-Burst mode (i.e. single shots).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I would still suggest to change Chip_ADC_SetSampleRate() and let it return the actually achieved sample rate (or at least return an error in such a case as mine).&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:29:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Too-many-IRQs-for-ADC-LPC4078/m-p/546073#M13189</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:29:55Z</dc:date>
    </item>
  </channel>
</rss>

