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    <title>LPC MicrocontrollersのトピックRe: Help on configuring PLL on LPC3131</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545399#M13057</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by BasicPoke on Tue May 10 12:01:50 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I don't know which mode the PLL is using in my example.&amp;nbsp; The code sets HP1_MODE = 1.&amp;nbsp; Does this mean 1a, 1b, 1c, or 1d?&amp;nbsp; The only mode that uses the post-divider P indicates that P can be set to 1 to 32, but then the table on page 288 shows values of P outside of this range (66 and 98).&amp;nbsp; I have tried the equations listed for Modes 1a, 1b, 1c, and 1d and none of them match table 298.&amp;nbsp; I have found that when I use settings from this table, my output frequency appears to match that in the table (CLOCK_OUT is Fout / 2).&amp;nbsp; The table works but I don't know why.&amp;nbsp; For example:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;&amp;nbsp; HP1_MDEC = 1023;&amp;nbsp;&amp;nbsp;&amp;nbsp; //M divider
&amp;nbsp; HP1_NDEC = 770;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //N divider
&amp;nbsp; HP1_PDEC = 10;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //P divider
&amp;nbsp; HP1_SELR = 0;
&amp;nbsp; HP1_SELI = 16;
&amp;nbsp; HP1_SELP = 7;
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Table 298 indicates Fout = 24 MHz and I measure 12 MHz on CLOCK_OUT, which I believe would be correct.&amp;nbsp; Can anyone shed some light on this?&amp;nbsp; Is it possible for me to use Fout = 12 MHz.&amp;nbsp; I don't see any logic here that tells me how to do this.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Ron&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:29:07 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:29:07Z</dc:date>
    <item>
      <title>Help on configuring PLL on LPC3131</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545398#M13056</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by BasicPoke on Tue May 10 08:50:34 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;On the LPC3131, can I please get some help on how to set up the PLL for a certain frequency.&amp;nbsp; I am not really understanding the documentation in the user manual UM10314.&amp;nbsp; Here is the sample code I have.&amp;nbsp; Do I only need to set the 3 dividers?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;&amp;nbsp; //PLL Init 180MHz
&amp;nbsp; HP1_MODE = 0x4;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //Power Down PLL

&amp;nbsp; HP1_FIN_SELECT = 0; //Select FFAST as Pll input clock
&amp;nbsp; HP1_MDEC = 8191;&amp;nbsp;&amp;nbsp;&amp;nbsp; //M divider
&amp;nbsp; HP1_NDEC = 770;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //N divider
&amp;nbsp; HP1_PDEC = 98;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //P divider

&amp;nbsp; HP1_SELR = 0;
&amp;nbsp; HP1_SELI = 16;
&amp;nbsp; HP1_SELP = 8;

&amp;nbsp; HP1_MODE = 1;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //Enable PLL

&amp;nbsp; while(!(HP1_STATUS &amp;amp; 1)); //Wait untill PLL locks&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Also, I am seeing 90 MHz on the CLOCK_OUT signal.&amp;nbsp; Is it normal for this to be the main clock divided by 2?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks for any help.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Ron&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:29:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545398#M13056</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:29:06Z</dc:date>
    </item>
    <item>
      <title>Re: Help on configuring PLL on LPC3131</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545399#M13057</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by BasicPoke on Tue May 10 12:01:50 MST 2016&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I don't know which mode the PLL is using in my example.&amp;nbsp; The code sets HP1_MODE = 1.&amp;nbsp; Does this mean 1a, 1b, 1c, or 1d?&amp;nbsp; The only mode that uses the post-divider P indicates that P can be set to 1 to 32, but then the table on page 288 shows values of P outside of this range (66 and 98).&amp;nbsp; I have tried the equations listed for Modes 1a, 1b, 1c, and 1d and none of them match table 298.&amp;nbsp; I have found that when I use settings from this table, my output frequency appears to match that in the table (CLOCK_OUT is Fout / 2).&amp;nbsp; The table works but I don't know why.&amp;nbsp; For example:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;TABLE border="1"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD bgcolor="#cacaca"&gt; &lt;PRE&gt;&amp;nbsp; HP1_MDEC = 1023;&amp;nbsp;&amp;nbsp;&amp;nbsp; //M divider
&amp;nbsp; HP1_NDEC = 770;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //N divider
&amp;nbsp; HP1_PDEC = 10;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; //P divider
&amp;nbsp; HP1_SELR = 0;
&amp;nbsp; HP1_SELI = 16;
&amp;nbsp; HP1_SELP = 7;
&lt;/PRE&gt; &lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Table 298 indicates Fout = 24 MHz and I measure 12 MHz on CLOCK_OUT, which I believe would be correct.&amp;nbsp; Can anyone shed some light on this?&amp;nbsp; Is it possible for me to use Fout = 12 MHz.&amp;nbsp; I don't see any logic here that tells me how to do this.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Thanks&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Ron&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:29:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545399#M13057</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:29:07Z</dc:date>
    </item>
    <item>
      <title>Re: Help on configuring PLL on LPC3131</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545400#M13058</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;SPAN&gt;bump&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 19 Jun 2016 01:10:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Help-on-configuring-PLL-on-LPC3131/m-p/545400#M13058</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-19T01:10:36Z</dc:date>
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