topic Re: LPC11xx main clock limit in LPC Microcontrollers

LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:16 GMT

Content originally posted in LPCWare by Zoltan on Fri Jun 01 04:38:07 MST 2012
The LPC11xx manual lists specifies the frequency limits of the VCO of the PLL. It also states the limit for the system clock.
However, I could not find any mention of the max. frequency of the main clock, that is, the output of the PLL's P divider and input for the system clock divider.

I wonder if someone from NXP could tell the limit on that clock line?

Thanks.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:16 GMT

Content originally posted in LPCWare by jdurand on Fri Jun 01 12:13:22 MST 2012
I believe the data sheet says 50MHz. My Code Red startup file sets it to 48MHz by default.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:17 GMT

Content originally posted in LPCWare by Zoltan on Fri Jun 01 15:43:24 MST 2012
Jerry,

Can you tell me where did you find it in the data sheet?

I know that the max system clock is 50MHz, that's clearly stated.
But I could not find the limit on the main clock. I went through the user manual and found nothing.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:18 GMT

Content originally posted in LPCWare by jdurand on Fri Jun 01 16:59:37 MST 2012
Ah, you mean the PLL output? Don't know what that is, for now I'm just leaving everything set to the default 48MHz.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:18 GMT

Content originally posted in LPCWare by atomicdog on Fri Jun 01 18:10:42 MST 2012
According to the Rev 6 user manual 'main clock (FCLKOUT)' needs to be less the 100 MHz.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:19 GMT

Content originally posted in LPCWare by Ex-Zero on Sat Jun 02 01:39:16 MST 2012
And it's really working.

<code>
#define SYSPLLCTRL_Val 0x00000007 //96 MHz main clock
#define SYSAHBCLKDIV_Val 0x00000002 //48 MHz system clock
</code>

CLKOUT is showing a 96 MHz main clock.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:20 GMT

Content originally posted in LPCWare by Ex-Zero on Sat Jun 02 01:40:20 MST 2012
Still don't know how to delete....

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:20 GMT

Content originally posted in LPCWare by Zoltan on Sat Jun 02 01:41:58 MST 2012
100MHz it is.

Thanks a lot!

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:21 GMT

Content originally posted in LPCWare by PhilYoung on Sat Jun 02 01:47:20 MST 2012
look in UM10398a.pdf, page 43.

The block diagram of this PLL is shown in Figure 7. The input frequency range is 10 MHz
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock and
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2xP by the programmable post divider to
create the output clock(s), or are sent directly to the output(s). The main output clock is
then divided by M by the programmable feedback divider to generate the feedback clock.
The output signal of the phase-frequency detector is also monitored by the lock detector,
to signal when the PLL has locked on to the input clock.

Remark: The divider values for P and M must be selected so that the PLL output clock
frequency FCLKOUT is lower than 100 MHz.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:21 GMT

Content originally posted in LPCWare by Zoltan on Sat Jun 02 05:48:01 MST 2012
OK, I'm getting blind, it seems.
I've read that chapter umpteen times (searching for the value) and missed that remark every time.
Thanks.

Re: LPC11xx main clock limit

lpcware — Wed, 15 Jun 2016 19:46:22 GMT

Content originally posted in LPCWare by purplexed on Mon Sep 08 00:28:47 MST 2014
I've tried

#define SYSPLLCTRL_Val 0x00000007 //96 MHz main clock
#define SYSAHBCLKDIV_Val 0x00000001 //96 MHz system clock

and system keeps on running...I don't understand. Someone can explain it?