LPC MicrocontrollersのトピックRe: Execute RAM code on-the-fly ISP mode

Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:20 GMT

Content originally posted in LPCWare by rzamuner on Wed Mar 09 02:09:30 MST 2016
Hi all,

I'm trying to execute a simple program that blink a led directly from RAM after download it through ISP command.
I download the program with WRITE to RAM command (W) in ISP mode and after that I send the command GO (G) with the address of the main but nothing happens.

Does the GO command set the program counter to the main address? Is there a way to solve this issue?
Please remember that I could not reset the chip.

I'm using LPC11A14 (CORTEX M0)

Regards and have a good day

Ric

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:21 GMT

Content originally posted in LPCWare by DF9DQ on Wed Mar 09 10:17:25 MST 2016
The GO command doesn't know anything about the binary you've downloaded, and will therefore only start exactly at the address you specify.

If you download an image that begins with a Cortex-M vector table, you need to know yourself where the entry address is, and specify it with the GO command. The vector table doesn't start with executable code, so jumping there would crash the CPU.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:21 GMT

Content originally posted in LPCWare by starblue on Thu Mar 10 01:33:42 MST 2016

Quote: DF9DQ
If you download an image that begins with a Cortex-M vector table, you need to know yourself where the entry address is, and specify it with the GO command. The vector table doesn't start with executable code, so jumping there would crash the CPU.

In such an image the second word (at offset 4) contains the Reset vector, which should be a good start address. You'll need to clear bit 0, which is not really part of the address (it signals thumb mode and is always set on Cortex-M).

Now according to the user manual the 'G' command expects a value at a word boundary (divisible by 4), which is a bit strange because the hardware only requires alignment to halfwords (divisible by 2). So if you find an address that is divisible by 2 but not by 4 you may be out of luck.

Note I haven't tried this myself.

Also, note that the image needs to be linked for running at the RAM address you are using. You can't take the same image that is used in flash memory.

*Edit*: Stack size could still be a problem, because this method wouldn't set up the stack properly, unless the image does that itself (normal images don't, as it is done by the hardware before anything else).

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:22 GMT

Content originally posted in LPCWare by rzamuner on Thu Mar 10 01:43:37 MST 2016
Hi guys,

thanks for the answer but I have no luck. After linking correctly to RAM and change the entry point, the program doesn't start with GO command.

In attach the map file and the cstartup_M.s file

I start the program passing to GO command the address of the main that is located ad 0x10000599 but this is not aligned to halwords or a word and the GO command fails.

So, is there a way to add some padding to align correctly? Is the entry point set correctly on cstartup file ?

Rgds and good day

cstartup_M.s

/**************************************************
 *
 * Part one of the system initialization code, contains low-level
 * initialization, plain thumb variant.
 *
 * Copyright 2011 IAR Systems. All rights reserved.
 *
 * $Revision: 47021 $
 *
 **************************************************/

;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;

        MODULE  ?cstartup

        ;; Forward declaration of sections.
        SECTION CSTACK:DATA:NOROOT(3)

        SECTION .intvec:CODE:NOROOT(2)

        EXTERN  main
        //EXTERN __iar_program_start

        PUBLIC  __vector_table
        PUBLIC  __vector_table_0x1c
        DATA


__vector_table
                DCD     sfe(CSTACK)                 ; Top of Stack
                //DCD     __iar_program_start
__vector_table_0x1c
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved


                ; External Interrupts
                DCD     GPIO0_IRQHandler      ; All GPIO pin can be routed to FLEX_INTx



;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
        THUMB
        SECTION .text:CODE:REORDER:NOROOT(1)

GPIO0_IRQHandler

Default_Handler:
        B Default_Handler
        
        SECTION .crp:CODE:ROOT(2)
        DATA
/* Code Read Protection
NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
                   - Copy RAM to flash command can not write to Sector 0.
                   - Erase command can erase Sector 0 only when all sectors
                     are selected for erase.
                   - Compare command is disabled.
                   - Read Memory command is disabled.
CRP2    0x87654321 - Read Memory is disabled.
                   - Write to RAM is disabled.
                   - "Go" command is disabled.
                   - Copy RAM to flash is disabled.
                   - Compare is disabled.
CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
                     by pulling PIO0_1 LOW is disabled if a valid user code is
                     present in flash sector 0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
*/
DCD0xFFFFFFFF

        END

and the .map file generated

###############################################################################
#                                                                             #
# IAR ELF Linker V6.30.6.53336/W32 for ARM              10/Mar/2016  09:31:34 #
# Copyright 2007-2012 IAR Systems AB.                                         #
#                                                                             #
#    Output file  =  D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\Exe\GettingStarted.out.tmp           #
#    Map file     =  D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\List\GettingStarted.map              #
#    Command line =  D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\Obj\cstartup_M.o                     #
#                    D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\Obj\main.o --redirect                #
#                    _Printf=_PrintfTiny --redirect _Scanf=_ScanfSmall -o     #
#                    D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\Exe\GettingStarted.out.tmp --map     #
#                    D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\Release\List\GettingStarted.map --config     #
#                    D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStarted\config\LPC11A14_Flash.icf --semihosting      #
#                    --inline --merge_duplicate_sections --vfe                #
#                                                                             #
#                                                                             #
###############################################################################

*******************************************************************************
*** RUNTIME MODEL ATTRIBUTES
***

CppFlavor       = *
__SystemLibrary = DLib


*******************************************************************************
*** PLACEMENT SUMMARY
***

"A1":  place at 0x10000000 { ro section .intvec };
"P1":  place in [from 0x10000200 to 0x100004ff] { ro };
"P2":  place in [from 0x10000500 to 0x10001de0] { rw, block CSTACK, block HEAP };
"P4":  place in [from 0x000002fc to 0x000002ff] { section .crp };

  Section            Kind        Address   Size  Object
  -------            ----        -------   ----  ------
"P4":                                       0x4
  P4 s0                       0x000002fc    0x4  <Init block>
    .crp             inited   0x000002fc    0x4  cstartup_M.o [1]
                            - 0x00000300    0x4

"A1":                                      0x20
  .intvec            ro code  0x10000000   0x20  cstartup_M.o [1]
                            - 0x10000020   0x20

"P1":                                     0x1c8
  .text              ro code  0x10000200   0x2e  copy_init3.o [4]
  .text              ro code  0x1000022e    0x2  cstartup_M.o [1]
  .text              ro code  0x10000230   0x2c  data_init3.o [4]
  .iar.init_table    const    0x1000025c   0x28  - Linker created -
  .text              ro code  0x10000284   0x16  cmain.o [4]
  .text              ro code  0x1000029c   0x14  exit.o [5]
  .text              ro code  0x100002b0    0xc  cstartup_M.o [4]
  .rodata            const    0x100002bc    0x0  bwt_init3c.o [4]
  Initializer bytes  ro data  0x100002bc    0x4  <for P4 s0>
  Initializer bytes  ro data  0x100002c0  0x108  <for P2 s1>
                            - 0x100003c8  0x1c8

"P2", part 1 of 2:                        0x108
  P2 s1                       0x10000500  0x108  <Init block>
    RAMCODE          inited   0x10000500   0xf4  main.o [1]
    .text            inited   0x100005f4    0xa  cexit.o [4]
    .text            inited   0x100005fe    0x8  exit.o [3]
                            - 0x10000608  0x108

"P2", part 2 of 2:                        0x800
  CSTACK                      0x10000608  0x800  <Block>
    CSTACK           uninit   0x10000608  0x800  <Block tail>
                            - 0x10000e08  0x800

Absolute sections, part 1 of 9:             0x4
  .noinit            uninit   0x40044000    0x4  main.o [1]
                            - 0x40044004    0x4

Absolute sections, part 2 of 9:            0x20
  .noinit            uninit   0x40044040    0x4  main.o [1]
  .noinit            uninit   0x40044044    0x4  main.o [1]
  .noinit            uninit   0x40044048    0x4  main.o [1]
  .noinit            uninit   0x4004404c    0x4  main.o [1]
  .noinit            uninit   0x40044050    0x4  main.o [1]
  .noinit            uninit   0x40044054    0x4  main.o [1]
  .noinit            uninit   0x40044058    0x4  main.o [1]
  .noinit            uninit   0x4004405c    0x4  main.o [1]
                            - 0x40044060   0x20

Absolute sections, part 3 of 9:             0x4
  .noinit            uninit   0x40048000    0x4  main.o [1]
                            - 0x40048004    0x4

Absolute sections, part 4 of 9:             0xc
  .noinit            uninit   0x40048070    0x4  main.o [1]
  .noinit            uninit   0x40048074    0x4  main.o [1]
  .noinit            uninit   0x40048078    0x4  main.o [1]
                            - 0x4004807c    0xc

Absolute sections, part 5 of 9:             0x4
  .noinit            uninit   0x40048080    0x4  main.o [1]
                            - 0x40048084    0x4

Absolute sections, part 6 of 9:             0x4
  .noinit            uninit   0x40048238    0x4  main.o [1]
                            - 0x4004823c    0x4

Absolute sections, part 7 of 9:             0x8
  .noinit            uninit   0x50002000    0x4  main.o [1]
  .noinit            uninit   0x50002004    0x4  main.o [1]
                            - 0x50002008    0x8

Absolute sections, part 8 of 9:             0x4
  .noinit            uninit   0x50002100    0x4  main.o [1]
                            - 0x50002104    0x4

Absolute sections, part 9 of 9:             0x4
  .noinit            uninit   0x50002200    0x4  main.o [1]
                            - 0x50002204    0x4


*******************************************************************************
*** INIT TABLE
***

          Address     Size
          -------     ----
Copy (__iar_copy_init3)
    1 source range, total size 0x4:
          0x100002bc    0x4
    1 destination range, total size 0x4:
          0x000002fc    0x4

Copy (__iar_copy_init3)
    1 source range, total size 0x108 (100% of destination):
          0x100002c0  0x108
    1 destination range, total size 0x106:
          0x10000500  0x106



*******************************************************************************
*** MODULE SUMMARY
***

    Module          ro code  rw code  ro data  rw data  rw data
                                                         (abs)
    ------          -------  -------  -------  -------  -------
D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\GettingStarted\Release\Obj: [1]
    cstartup_M.o         34        4        4
    main.o                       244      244                76
    -----------------------------------------------------------
    Total:               34      248      248                76

command line: [2]
    -----------------------------------------------------------
    Total:

dl6M_tln.a: [3]
    exit.o                         8        8
    -----------------------------------------------------------
    Total:                         8        8

rt6M_tl.a: [4]
    bwt_init3c.o
    cexit.o                       10       10
    cmain.o              22
    copy_init3.o         46
    cstartup_M.o         12
    data_init3.o         44
    -----------------------------------------------------------
    Total:              124       10       10

shb_l.a: [5]
    exit.o               20
    -----------------------------------------------------------
    Total:               20

    Gaps                  2
    Linker created                         42    2 048
---------------------------------------------------------------
    Grand Total:        180      266      308    2 048       76


*******************************************************************************
*** ENTRY LIST
***

Entry                    Address  Size  Type      Object
-----                    -------  ----  ----      ------
?main                 0x10000285        Code  Gb  cmain.o [4]
CSTACK$$Base          0x10000608         --   Gb  - Linker created -
CSTACK$$Limit         0x10000e08         --   Gb  - Linker created -
GpioInit              0x10000537  0x20  Code  Gb  main.o [1]
InitClock             0x10000501  0x36  Code  Gb  main.o [1]
Region$$Table$$Base   0x1000025c         --   Gb  - Linker created -
Region$$Table$$Limit  0x10000284         --   Gb  - Linker created -
_A_IOCON_P0_16        0x40044040   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_17        0x40044044   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_18        0x40044048   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_19        0x4004404c   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_20        0x40044050   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_21        0x40044054   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_22        0x40044058   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_23        0x4004405c   0x4  Data  Gb  main.o [1]
_A_IOCON_RESET_P0_0   0x40044000   0x4  Data  Gb  main.o [1]
_A_MAINCLKSEL         0x40048070   0x4  Data  Gb  main.o [1]
_A_MAINCLKUEN         0x40048074   0x4  Data  Gb  main.o [1]
_A_P0DIR              0x50002000   0x4  Data  Gb  main.o [1]
_A_P0PORT             0x50002100   0x4  Data  Gb  main.o [1]
_A_P0SET              0x50002200   0x4  Data  Gb  main.o [1]
_A_P1DIR              0x50002004   0x4  Data  Gb  main.o [1]
_A_PDRUNCFG           0x40048238   0x4  Data  Gb  main.o [1]
_A_SYSAHBCLKCTRL      0x40048080   0x4  Data  Gb  main.o [1]
_A_SYSAHBCLKDIV       0x40048078   0x4  Data  Gb  main.o [1]
_A_SYSMEMREMAP        0x40048000   0x4  Data  Gb  main.o [1]
__cmain               0x10000285        Code  Gb  cmain.o [4]
__exit                0x1000029d  0x14  Code  Gb  exit.o [5]
__iar_SB              0x100002bc        Data  Gb  bwt_init3c.o [4]
__iar_copy_init3      0x10000201  0x2e  Code  Gb  copy_init3.o [4]
__iar_data_init3      0x10000231  0x2c  Code  Gb  data_init3.o [4]
__iar_program_start   0x100002b1        Code  Gb  cstartup_M.o [4]
__vector_table        0x10000000        Data  Gb  cstartup_M.o [1]
__vector_table_0x1c   0x10000004        Data  Gb  cstartup_M.o [1]
_call_main            0x10000291        Code  Gb  cmain.o [4]
_exit                 0x100005f5        Code  Gb  cexit.o [4]
_main                 0x10000297        Code  Gb  cmain.o [4]
exit                  0x100005ff   0x8  Code  Gb  exit.o [3]
main                  0x10000559  0x6e  Code  Gb  main.o [1]


[1] = D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\GettingStarted\Release\Obj
[2] = command line
[3] = dl6M_tln.a
[4] = rt6M_tl.a
[5] = shb_l.a

    180 bytes of readonly  code memory
    266 bytes of readwrite code memory
    308 bytes of readonly  data memory
  2 048 bytes of readwrite data memory (+ 76 absolute)

Errors: none
Warnings: none

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:23 GMT

Content originally posted in LPCWare by vtw.433e on Thu Mar 10 02:16:53 MST 2016
A few things here:

1. The bottom bit being set on the PC indicates that it is a Thumb instruction. All Cortex-M based MCUs use the Thumb instruction set, so this is completely normal. It has nothing to do with alignment (remove the bottom bit to work out the alignment of instructions)

2. In your vector table, you have commented out the application entry point (2nd entry in the vector table). This may not matter if you are using the start address directly, but it does mean your vector table is now out by 1 DWORD and so the correct interrupt handlers will not be called

3. The entry point of your application is NOT main. There is essential startup code that MUST run before main. The entry point is __iar_program_start so use the address of that in your GO command

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:23 GMT

Content originally posted in LPCWare by starblue on Thu Mar 10 02:21:28 MST 2016
Did you edit out __iar_program_start ?
For the addresses you need to clear bit 0 (subtract 1). So that would be 0x10000598.
But jumping directly to main would bypass initialization, so depending on circumstances it may or may not work. __iar_program_start sounds better (but I don't know), or maybe one of the other functions called *main.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:24 GMT

Content originally posted in LPCWare by rzamuner on Thu Mar 10 02:50:10 MST 2016

Quote: starblue
Did you edit out __iar_program_start ?

what do you mean with edit __iar_program_start ? redefined the function?

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:25 GMT

Content originally posted in LPCWare by rzamuner on Thu Mar 10 02:58:12 MST 2016
I'll give you just another information that could be useful: the program that I try to run from RAM is not programmed into flash.

The program looks like a flashloader and I need it to program EEPROM through IAP.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:25 GMT

Content originally posted in LPCWare by vtw.433e on Thu Mar 10 03:21:02 MST 2016
Read my earlier post, which explains (some of) what you are doing wrong.

https://www.lpcware.com/content/forum/execute-ram-code-fly-isp-mode#comment-1149851

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:26 GMT

Content originally posted in LPCWare by rzamuner on Thu Mar 10 03:41:36 MST 2016
Hi vtw.433e

I follow your step:
- decomment entry point in the vector table
- pass to the GO function the address of __iar_program_start

but it still not work!! The pin that I used for led blinking does not toggle.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:26 GMT

Content originally posted in LPCWare by ElecoLPC on Thu Mar 10 09:18:32 MST 2016
Hi all,
I'm learning to program, where can I find a guide that explains well what you are doing? because I would also like to run a program into RAM.

Thanks too much.

Lorenzo.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:27 GMT

Content originally posted in LPCWare by vtw.433e on Thu Mar 10 09:26:06 MST 2016
You are going to have to use a debugger to find out why your application is not working - it may have nothing to do with the GO command... For example, where is your stack?

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:28 GMT

Content originally posted in LPCWare by rzamuner on Mon Mar 14 10:22:43 MST 2016
Hi guys,

I've double checked my program and try it into flash to avoid crashes. The program run correctly without any sort of problem.
I used the address of entry_point function passed to ISP GO command but nothing happens.

Following the main and the map file generated after make.


//main.c
#include "includes.h"

/** external data **/

/** internal functions **/

/** public functions **/

void CopyInterruptToSRAM(void)
{
  unsigned int * flashPtr, * ramPtr;
  unsigned int * uLimit = (unsigned int *) 0x200;
  
  ramPtr = (unsigned int *)0x10000000;//load RAM starting at 0x10000000,
  flashPtr = (unsigned int *)0x00;//start of interrupt vector table
  while(flashPtr < uLimit)
  {
    *ramPtr = *flashPtr;
    ramPtr++;
    flashPtr++;
  }
}

/*************************************************************************
* Function Name: InitClock
* Parameters: pllclock - PLL clock, ahbdiv - AHB divider
* Return: void
*
* Description: Initialize PLL to desired clock and AHB divider
*              Sys clock is Sys PLL output
*
*************************************************************************/
void InitClock()
{
  /* Enable XTAL Oscilator */
  PDRUNCFG_bit.XTAL_PD = 1;
  /* Enable Internal RC oscilator */
  PDRUNCFG_bit.IRC_PD = 0;
  /* Select internal RC oscilator for SYS clock source */
  MAINCLKUEN = 0;
  MAINCLKSEL = 0;
  MAINCLKUEN = 1;
  
  MAINCLKUEN = 0;
  MAINCLKSEL = 1;
  MAINCLKUEN = 1;
}

/*************************************************************************
* Function Name: GpioInit
* Parameters: void
* Return: void
*
* Description: Reset all GPIO pins to default: primary function
*
*************************************************************************/
void GpioInit(void)
{
  /* Set to inputs */
  P0DIR = 0;
  P1DIR = 0;
  
  /* Reset all GPIO pins to default primary function */
  
  IOCON_P0_16 = 0x90;
  IOCON_P0_17 = 0x90;
  IOCON_P0_18 = 0x90;
  IOCON_P0_19 = 0x90;
  IOCON_P0_20 = 0x90;
  IOCON_P0_21 = 0x90;
  IOCON_P0_22 = 0x90;
  IOCON_P0_23 = 0x90;
 
}

#pragma language=extended
#pragma segment="CSTACK"

void entry_point(void);

typedef void( *intfunc )( void );
typedef union { intfunc __fun; void * __ptr; } intvec_elem;

// The vector table is normally located at address 0.
// When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
// If you need to define interrupt service routines,
// make a copy of this file and include it in your project.
// The name "__vector_table" has special meaning for C-SPY:
// it is where the SP start value is found, and the NVIC vector
// table register (VTOR) is initialized to this address if != 0.

#pragma location = ".intvec"
const intvec_elem __vector_table[] =
{
  { .__ptr = __sfe( "CSTACK" ) },
  entry_point,
};

/*************************************************************************
* Function Name: main
* Parameters: none
*
* Return: none
*
* Description: main
*
*************************************************************************/
int main(void)
{
  Int8U counter=0;
  
  /* Init clock */
  InitClock();
  /* Enable GPIO Clock */
  SYSAHBCLKCTRL_bit.GPIO = 1;
  /* Enable IOCON Clock */
  SYSAHBCLKCTRL_bit.IOCON = 1;
  /* Set all pins as input ports */
  GpioInit();
  /* Init LED Ports */
  LEDS_OFF();
  LEDS_DIR |= LEDS_MASK;

  /* Main loop */
  while(1)
  {
      
      /* Lights-up next LED                     */
      /* if USER button is pressed, invert LEDs */
      LEDS_OFF();
      if(!(USER_PORT & USER_MASK))
      {
        LEDS_ON(~(1 << (counter++%8)));
      }
      else
      {
        LEDS_ON(1 << (counter++%8));
      }
      
      for (int i = 0; i < 100000; i++)
        asm("NOP");
      
    }
}

#pragma required=__vector_table
void entry_point()
{
  main();
}

###############################################################################
#                                                                             #
# IAR ELF Linker V6.30.6.53336/W32 for ARM              14/Mar/2016  17:34:08 #
# Copyright 2007-2012 IAR Systems AB.                                         #
#                                                                             #
#    Output file  =  D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStartedCleanedRAM\Flash                              #
#                    Debug\Exe\GettingStarted.out.tmp                         #
#    Map file     =  D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStartedCleanedRAM\Flash                              #
#                    Debug\List\GettingStarted.map                            #
#    Command line =  "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash Debug\Obj\cstartup_M.o"     #
#                    "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash Debug\Obj\drv_hd44780.o"    #
#                    "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash Debug\Obj\drv_hd44780_l.o"  #
#                    "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash Debug\Obj\drv_nvic.o"       #
#                    "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash Debug\Obj\main.o"           #
#                    --redirect _Printf=_PrintfTiny --redirect                #
#                    _Scanf=_ScanfSmall -o "D:\Desktop\arm\examples\NXP\LPC11 #
#                    xx\IAR-LPC-11A14-SK\GettingStartedCleanedRAM\Flash       #
#                    Debug\Exe\GettingStarted.out.tmp" --map                  #
#                    "D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Ge #
#                    ttingStartedCleanedRAM\Flash                             #
#                    Debug\List\GettingStarted.map" --config                  #
#                    D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\Get #
#                    tingStartedCleanedRAM\config\LPC11A14_Flash.icf          #
#                    --semihosting --entry entry_point --inline               #
#                    --merge_duplicate_sections --vfe                         #
#                                                                             #
#                                                                             #
###############################################################################

*******************************************************************************
*** RUNTIME MODEL ATTRIBUTES
***

CppFlavor       = *
__SystemLibrary = DLib


*******************************************************************************
*** PLACEMENT SUMMARY
***

"P1":  place in [from 0x10000200 to 0x100003ff] { section .intvec };
"P2":  place in [from 0x10000200 to 0x10001fdf] {
          section .cstartup, ro, rw, block CSTACK, block HEAP };

  Section   Kind        Address   Size  Object
  -------   ----        -------   ----  ------
"P1":                              0x8
  .intvec   const    0x10000200    0x8  main.o [1]
                   - 0x10000208    0x8

"P2":                            0x8d8
  .text     ro code  0x10000208   0xd4  main.o [1]
  CSTACK             0x100002e0  0x800  <Block>
    CSTACK  uninit   0x100002e0  0x800  <Block tail>
                   - 0x10000ae0  0x8d8

Absolute sections, part 1 of 8:   0x20
  .noinit   uninit   0x40044040    0x4  main.o [1]
  .noinit   uninit   0x40044044    0x4  main.o [1]
  .noinit   uninit   0x40044048    0x4  main.o [1]
  .noinit   uninit   0x4004404c    0x4  main.o [1]
  .noinit   uninit   0x40044050    0x4  main.o [1]
  .noinit   uninit   0x40044054    0x4  main.o [1]
  .noinit   uninit   0x40044058    0x4  main.o [1]
  .noinit   uninit   0x4004405c    0x4  main.o [1]
                   - 0x40044060   0x20

Absolute sections, part 2 of 8:    0x8
  .noinit   uninit   0x40048070    0x4  main.o [1]
  .noinit   uninit   0x40048074    0x4  main.o [1]
                   - 0x40048078    0x8

Absolute sections, part 3 of 8:    0x4
  .noinit   uninit   0x40048080    0x4  main.o [1]
                   - 0x40048084    0x4

Absolute sections, part 4 of 8:    0x4
  .noinit   uninit   0x40048238    0x4  main.o [1]
                   - 0x4004823c    0x4

Absolute sections, part 5 of 8:    0x8
  .noinit   uninit   0x50002000    0x4  main.o [1]
  .noinit   uninit   0x50002004    0x4  main.o [1]
                   - 0x50002008    0x8

Absolute sections, part 6 of 8:    0x4
  .noinit   uninit   0x50002100    0x4  main.o [1]
                   - 0x50002104    0x4

Absolute sections, part 7 of 8:    0x4
  .noinit   uninit   0x50002200    0x4  main.o [1]
                   - 0x50002204    0x4

Absolute sections, part 8 of 8:    0x4
  .noinit   uninit   0x50002280    0x4  main.o [1]
                   - 0x50002284    0x4



*******************************************************************************
*** MODULE SUMMARY
***

    Module          ro code  ro data  rw data  rw data
                                                (abs)
    ------          -------  -------  -------  -------
D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\GettingStartedCleanedRAM\Flash Debug\Obj: [1]
    main.o              212        8                68
    --------------------------------------------------
    Total:              212        8                68

    Linker created                      2 048
------------------------------------------------------
    Grand Total:        212        8    2 048       68


*******************************************************************************
*** ENTRY LIST
***

Entry                    Address  Size  Type      Object
-----                    -------  ----  ----      ------
CSTACK$$Base          0x100002e0         --   Gb  - Linker created -
CSTACK$$Limit         0x10000ae0         --   Gb  - Linker created -
GpioInit              0x1000022f  0x1e  Code  Gb  main.o [1]
InitClock             0x10000209  0x26  Code  Gb  main.o [1]
Region$$Table$$Base   0x00000000         --   Gb  - Linker created -
Region$$Table$$Limit  0x00000000         --   Gb  - Linker created -
_A_IOCON_P0_16        0x40044040   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_17        0x40044044   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_18        0x40044048   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_19        0x4004404c   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_20        0x40044050   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_21        0x40044054   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_22        0x40044058   0x4  Data  Gb  main.o [1]
_A_IOCON_P0_23        0x4004405c   0x4  Data  Gb  main.o [1]
_A_MAINCLKSEL         0x40048070   0x4  Data  Gb  main.o [1]
_A_MAINCLKUEN         0x40048074   0x4  Data  Gb  main.o [1]
_A_P0CLR              0x50002280   0x4  Data  Gb  main.o [1]
_A_P0DIR              0x50002000   0x4  Data  Gb  main.o [1]
_A_P0PORT             0x50002100   0x4  Data  Gb  main.o [1]
_A_P0SET              0x50002200   0x4  Data  Gb  main.o [1]
_A_P1DIR              0x50002004   0x4  Data  Gb  main.o [1]
_A_PDRUNCFG           0x40048238   0x4  Data  Gb  main.o [1]
_A_SYSAHBCLKCTRL      0x40048080   0x4  Data  Gb  main.o [1]
__vector_table        0x10000200   0x8  Data  Gb  main.o [1]
entry_point           0x100002d5   0x8  Code  Gb  main.o [1]
main                  0x10000251  0x5e  Code  Gb  main.o [1]


[1] = D:\Desktop\arm\examples\NXP\LPC11xx\IAR-LPC-11A14-SK\GettingStartedCleanedRAM\Flash Debug\Obj
[2] = command line
[3] = dl6M_tln.a
[4] = rt6M_tl.a
[5] = shb_l.a

    212 bytes of readonly  code memory
      8 bytes of readonly  data memory
  2 048 bytes of readwrite data memory (+ 68 absolute)

Errors: none
Warnings: none

The ISP GO command is send with this syntax "GO 0x100002d4 T"

Rgds

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:28 GMT

Content originally posted in LPCWare by R2D2 on Mon Mar 14 12:23:20 MST 2016

Quote: rzamuner

void InitClock()
{
  /* Enable XTAL Oscilator */
  PDRUNCFG_bit.XTAL_PD = 1;
  /* Enable Internal RC oscilator */
  PDRUNCFG_bit.IRC_PD = 0;
  /* Select internal RC oscilator for SYS clock source */
  MAINCLKUEN = 0;
  MAINCLKSEL = 0;
  MAINCLKUEN = 1;
  
  MAINCLKUEN = 0;
  MAINCLKSEL = 1;
  MAINCLKUEN = 1;
}

So what kind of clock source are you trying to use here?

Why is there no wait loop??

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:29 GMT

Content originally posted in LPCWare by rzamuner on Tue Mar 15 01:11:39 MST 2016
Internal RC oscillator. The instruction PDRUNCFG_bit.IRC_PD = 0; sets the IRC clock source and PDRUNCFG_bit.XTAL_PD = 1; disables XTAL Oscillator.

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:29 GMT

Content originally posted in LPCWare by R2D2 on Tue Mar 15 02:41:46 MST 2016

Quote: rzamuner
Internal RC oscillator. The instruction PDRUNCFG_bit.IRC_PD = 0; sets the IRC clock source and PDRUNCFG_bit.XTAL_PD = 1; disables XTAL Oscillator.

I'm familiar with this bits...

  MAINCLKUEN = 0;
  MAINCLKSEL = 0;
  MAINCLKUEN = 1;
  
  MAINCLKUEN = 0;
  MAINCLKSEL = 1;
  MAINCLKUEN = 1;

That's the funny part of your code to think about

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:30 GMT

Content originally posted in LPCWare by rzamuner on Tue Mar 15 03:01:26 MST 2016
I removed the last 3 instruction because they set PLL instead of internal clock. But it does not change the behaviour!!
Do you think that the previous error was the reason of a cpu crash ?

Re: Execute RAM code on-the-fly ISP mode

lpcware — Wed, 15 Jun 2016 19:44:31 GMT

Content originally posted in LPCWare by rzamuner on Wed Mar 16 05:15:52 MST 2016
Now it works fine. I've just move the code in middle RAM address. The problem is now another one. ReinvokeIsp function does not work! I've got a CPU fault also when I run the program from FLASH. Any suggestion ? This is the code that I use for reinvoking ISP

typedef unsigned int (*IAP)(unsigned int[], unsigned int[]);
static const IAP iap_entry = (IAP) IAP_ADDRESS;

static void iap_reinvoke_isp(void) {
  unsigned int command[5];
  unsigned int result[4];
  
  /* Set stack pointer to ROM value (reset default) */
  __set_MSP(*((Int32U *) 0x1FFF0000));
  
  command[0] = 57;
  iap_entry(command, result);
  
  /* Never return from here */
}

Thanks

Re: Execute RAM code on-the-fly ISP mode

lpcware — Sun, 19 Jun 2016 01:04:28 GMT

bump