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    <title>LPC MicrocontrollersのトピックRe: Ethernet Interrupt Issue</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-Interrupt-Issue/m-p/542445#M12480</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Rakutaro on Wed Mar 14 23:08:50 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regarding this issue, I've fixed it.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I've cleared both the RSF and TSF bits in the DMA Operation Mode Register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When these bits are set to 1, the interrupt didn't occur over 203 bytes PING.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;When these bits are set to 0, the interrupt occurs correctly.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Therefore, it is closed for this topic.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Rakutaro&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:26:06 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:26:06Z</dc:date>
    <item>
      <title>Ethernet Interrupt Issue</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-Interrupt-Issue/m-p/542444#M12479</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Rakutaro on Tue Mar 13 02:47:54 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'd like to know the MAC behavior of LPC1850.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I couldn't find the topic in this forum.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt; &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm making an ethernet driver with the using ISR.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm facing a trouble for the ISR behavior.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In case of PING from PC side, it's working well.(64 bytes)&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;However, in case of 203bytes PING, the MAC doesn't work.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;In case of 202bytes PING, the MAC is working well.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;203 bytes means for the following caliculation.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;payload 203 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;preamble 8 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;IP tracks 42 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;FCS 4 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;total 257 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;202 bytes means for the following caliculation.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;payload 202 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;preamble 8 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;IP tracks 42 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;FCS 4 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;total 256 bytes&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a concern about internal RXFIFO size limitation as 256 bytes.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I've tried the both ringed buffer and chained buffer, the results were same.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The problem looks like a related both DMA descriptor and size limitation for the internal RxFIFO with the using interrupt.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I've also checked sample code in the lpcware site, the code is using polling technic for the receive side.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;It was no trouble found for any byte size. Why?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'd like to use the interrupt for the performance.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Therefore, I'd like to know the behavior whether the MAC with interrupt is abnormality, or not.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Kindly Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Raku&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:26:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-Interrupt-Issue/m-p/542444#M12479</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:26:05Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet Interrupt Issue</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-Interrupt-Issue/m-p/542445#M12480</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Rakutaro on Wed Mar 14 23:08:50 MST 2012&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regarding this issue, I've fixed it.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I've cleared both the RSF and TSF bits in the DMA Operation Mode Register.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When these bits are set to 1, the interrupt didn't occur over 203 bytes PING.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;When these bits are set to 0, the interrupt occurs correctly.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Therefore, it is closed for this topic.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Rakutaro&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:26:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-Interrupt-Issue/m-p/542445#M12480</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:26:06Z</dc:date>
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