topic Re: LPC1115FBD48/303 CT32B0CAP0 problem in LPC Microcontrollers

LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:56 GMT

Content originally posted in LPCWare by assembled on Sat Oct 18 07:49:41 MST 2014
Hi, everyone.

I have stumbled upon some really strange behaviour of the LPC1115FBD48/303.

I am using CT32B0 cap0 and cap1 to capture quadrature signal. The problem is that p1_5 cap0 function is working as intended and p2_9 cap0 simply does not work. I am sure I set up everything as per manual, but counter value never gets written to cr0 and interrupt is never generated by cap0 while cap1 functions as intended, reading p2_9 returns correct pin data. If I change p1_5 function to cap0 and change nothing else, interrupt gets generated by p1_5 state and cr0 gets counter value.

I have checked every rellevant register using debugging and everything should work, but just does not.

Please advise.

Thanks.

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:57 GMT

Content originally posted in LPCWare by LabRat on Sat Oct 18 07:55:43 MST 2014

Quote: assembled
I am sure I set up everything as per manual...

I have checked every rellevant register using debugging and everything should work, but just does not.

Please advise.

:quest:

So what do you expect now?

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:57 GMT

Content originally posted in LPCWare by assembled on Sat Oct 18 08:13:29 MST 2014

Quote: LabRat

Quote: assembled
I am sure I set up everything as per manual...

I have checked every rellevant register using debugging and everything should work, but just does not.

Please advise.

:quest:

So what do you expect now?

Technical support. Or request to provide certain additional information.

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:58 GMT

Content originally posted in LPCWare by LabRat on Sat Oct 18 08:28:43 MST 2014

Quote: assembled

Technical support. Or request to provide certain additional information.

Could be useful to post your code / project, at least if you a using a toolchain / library like LPCXpresso / LPCopen...

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:59 GMT

Content originally posted in LPCWare by assembled on Sun Oct 19 01:31:44 MST 2014
Thank you for your reply. I am using LPCXpresso and a SWD debugger.

Here are the important code snippets:

void Timer32InterrupterInit()
{
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);

//P2_11, input, hysteresis, passive, CAP1 function
SetupGPIO(2, 11, 0,
0b111 << 0 | 0b11 << 3 | (1<<5) | 1 << 10,
0x2 << 0   | 0x0 << 3  | (1<<5) | 0 << 10);
//P2_11, input, hysteresis, passive, CAP0 function
SetupGPIO(2, 9, 0,
0b111 << 0 | 0b11 << 3 | (1<<5) | 1 << 10,
0x1 << 0   | 0x0 << 3  | (1<<5) | 0 << 10);

//CAP0/1 rising edge should trigger interrupt and write TC to CR0/1
LPC_TMR32B0->CCR = 0b101101;

//reset timer on rising edge of CAP1
LPC_TMR32B0->CTCR = 0x2 << 5 | 0x1 << 4;

//in case of overflow
LPC_TMR32B0->MR0 = INTERRUPTER_TIMEOUT;
LPC_TMR32B0->MCR = 0b001;/* Interrupt and Reset on MR0 */

NVIC_EnableIRQ(TIMER_32_0_IRQn);

LPC_TMR32B0->TCR = 1;
return;
}

void TIMER32_0_IRQHandler(void)
{
RawData.lygis[1] = GetGPIOBit(2,11);
RawData.lygis[0] = GetGPIOBit(2,9);

if(LPC_TMR32B0->IR & 0x1) {
LPC_TMR32B0->IR = 0x1;
}
if(LPC_TMR32B0->IR & (1 << (4 + 1))) {
LPC_TMR32B0->IR = (1 << (4 + INTERRUPTER_A_CAP));
}
if (LPC_TMR32B0->IR & (1 << (4 + INTERRUPTER_B_CAP))) {
LPC_TMR32B0->IR = (1 << (4 + INTERRUPTER_B_CAP));
}
}

I have checked peripherals view for register values and everything is as set above (see attachment). CAP1 is triggering interrupt, IRQ handler gets executed, I can see changing states of P2_11 and P2_9 both within handler and in peripherals view. Unfortunately CR0 is always 0 and CAP0 interrupt never happens. If I set P1_5 function to CAP0, everything works. I have and older PCB version where P1_5 is used instead of P2_9 and it works perfectly.

What am I missing?

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:42:59 GMT

Content originally posted in LPCWare by LabRat on Sun Oct 19 02:11:59 MST 2014

Quote: assembled
Here are the important code snippets..

No, they are not. You are using library functions...

And of course reading GPIOs in IRQ is nonsense.

RawData.lygis[1] = GetGPIOBit(2,11);
RawData.lygis[0] = GetGPIOBit(2,9);

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:00 GMT

Content originally posted in LPCWare by assembled on Sun Oct 19 04:30:00 MST 2014
Here is the main.c file. I have put everything inside it to make it simple to follow. No libraries except CMSIS stuff.

Interrupt is requested when PIO2_11 or PIO1_5 is pulled down and not requested by PIO2_9.


#include "driver_config.h"
#include "target_config.h"

uint32_t timeTick = 0;
uint32_t stopTick = 0;

void TIMER32_0_IRQHandler(void)
{
//overflow
if(LPC_TMR32B0->IR & 0x1) {
LPC_TMR32B0->IR = 0x1;
}
//CAP1
if(LPC_TMR32B0->IR & (1 << 5)) {
LPC_TMR32B0->IR = (1 << 5);
}
//CAP0
if (LPC_TMR32B0->IR & (1 << 4)) {
LPC_TMR32B0->IR = (1 << 4);
}
}

int main(void) {
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9);
LPC_IOCON->PIO2_11 = 0x2 << 0   | 0x0 << 3  | (1<<5) | 0 << 10;
LPC_IOCON->PIO2_9  = 0x1 << 0   | 0x0 << 3  | (1<<5) | 0 << 10;
LPC_IOCON->PIO1_5  = 0x2 << 0   | 0x0 << 3  | (1<<5) | 0 << 10;

LPC_TMR32B0->CCR = 0b101101;
LPC_TMR32B0->CTCR = 0x2 << 5 | 0x1 << 4;
LPC_TMR32B0->MR0 = SystemCoreClock;
LPC_TMR32B0->MCR = 0b001;/* Interrupt on MR0 */
NVIC_EnableIRQ(TIMER_32_0_IRQn);
LPC_TMR32B0->TCR = 1;

while (1) /* Loop forever */
{
__WFI();
}
}

Project attached.

Regarding GPIO reading inside IRQ. What is the appropriate way of getting GPIO values after interrupt condition?

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:00 GMT

Content originally posted in LPCWare by assembled on Sun Oct 19 04:52:44 MST 2014
I have tested this project on another board with different layout but same IC. Completely same behavior.

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:01 GMT

Content originally posted in LPCWare by assembled on Sun Oct 19 05:13:34 MST 2014
Another sample project, same main() and IRQ, but CMSIS 2.0 (prievous was CMSIS 1.3). Same behavior.

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:02 GMT

Content originally posted in LPCWare by LabRat on Sun Oct 19 05:28:11 MST 2014
Did you change IOCON_CT32B0_CAP0_LOC?

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:02 GMT

Content originally posted in LPCWare by assembled on Sun Oct 19 06:00:45 MST 2014

Quote: LabRat
Did you change IOCON_CT32B0_CAP0_LOC?

Certainly not. Thank you good sir for solving my problem.

Never noticed those *_LOC registers before.
Thats what you get for skimming manuals instead of reading them thoroughly. Last 7 IOCON registers are not even in the LPC11xx.h file, LPC_IOCON_TypeDef, supplied with CMSIS 1.3 or CMSIS 2.0.

Complete fix:

typedef struct
{
  __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
       uint32_t RESERVED0[1];
  __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
  __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0  (R/W) */
  __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
  __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
       uint32_t RESERVED1[1];
  __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */

  __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
  __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
  __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
  __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
  __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
  __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
  __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
  __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */

  __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
  __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
  __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
  __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
  __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
  __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
  __IO uint32_t PIO2_10;                /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
  __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */

  __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
  __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
  __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
  __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
  __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
  __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
  __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
  __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */

  __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
  __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
  __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
  __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
  __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
  __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
  __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
  __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */

  __IO uint32_t PIO1_5;                 /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
  __IO uint32_t PIO1_6;                 /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
  __IO uint32_t PIO1_7;                 /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
  __IO uint32_t PIO3_3;                 /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
  __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
  __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
  __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
  __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */

  __IO uint32_t CT16B0_CAP0_LOC; /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
  __IO uint32_t SCK1_LOC; /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
  __IO uint32_t MISO1_LOC; /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
  __IO uint32_t MOSI1_LOC; /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
  __IO uint32_t CT32B0_CAP0_LOC; /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
  __IO uint32_t RXD_LOC; /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
} LPC_IOCON_TypeDef;

and then simply

LPC_IOCON->CT32B0_CAP0_LOC = 1;

and everything works as intended.

Re: LPC1115FBD48/303 CT32B0CAP0 problem

lpcware — Wed, 15 Jun 2016 19:43:03 GMT

Content originally posted in LPCWare by LabRat on Sun Oct 19 06:23:34 MST 2014

Quote: assembled
Last 7 IOCON registers are not even in the LPC11xx.h file, LPC_IOCON_TypeDef, supplied with CMSIS 1.3 or CMSIS 2.0.

Older LPC11xx chips can't switch capture inputs, so probably we have to wait a few years before this registers find their way into official libraries :)