LPC MicrocontrollersのトピックThe spec clarifying for LPC185x. https://community.nxp.com/t5/LPC-Microcontrollers/The-spec-clarifying-for-LPC185x/m-p/540857#M12150 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by CH Wu on Sun Aug 30 18:44:23 MST 2015</STRONG><BR /><SPAN>Hello NXP team,</SPAN><BR /><BR /><SPAN>I have few questions regarding the spec description of LPC185x.</SPAN><BR /><SPAN>I want NXP member feedback me these questions because that are very important to us.</SPAN><BR /><BR /><SPAN>1.There are many descriptions in the user manual as following but didn’t descript the “O”. What is the “O” meaning for reset state of GPIO?</SPAN><BR /><SPAN>[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset without boot code operation.</SPAN><BR /><SPAN>2.The reset state was descripted in user manual for GPIO status indication. Does the “Reset state” mean the reset pin keeping at low?</SPAN><BR /><SPAN>3.What is the meaning for normal drive strength &amp; high drive strength?</SPAN><BR /><SPAN>I captured the following description from UM10430 for question 3.</SPAN><BR /><SPAN>[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength.</SPAN><BR /><SPAN>[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels, and hysteresis; high drive strength.</SPAN><BR /><SPAN>4.The P3_2 is “OL” during “Reset state” descripted in UM10430. What are the configurations of I/O pas? I referred to the block diagram of the I/O pad but I can’t figure out the configurations.</SPAN><BR /><SPAN>Please refer to the Fig. 34. Block diagram of the I/O pad of UM10430.</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:27:10 GMT lpcware 2016-06-15T18:27:10Z The spec clarifying for LPC185x. https://community.nxp.com/t5/LPC-Microcontrollers/The-spec-clarifying-for-LPC185x/m-p/540857#M12150 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by CH Wu on Sun Aug 30 18:44:23 MST 2015</STRONG><BR /><SPAN>Hello NXP team,</SPAN><BR /><BR /><SPAN>I have few questions regarding the spec description of LPC185x.</SPAN><BR /><SPAN>I want NXP member feedback me these questions because that are very important to us.</SPAN><BR /><BR /><SPAN>1.There are many descriptions in the user manual as following but didn’t descript the “O”. What is the “O” meaning for reset state of GPIO?</SPAN><BR /><SPAN>[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset without boot code operation.</SPAN><BR /><SPAN>2.The reset state was descripted in user manual for GPIO status indication. Does the “Reset state” mean the reset pin keeping at low?</SPAN><BR /><SPAN>3.What is the meaning for normal drive strength &amp; high drive strength?</SPAN><BR /><SPAN>I captured the following description from UM10430 for question 3.</SPAN><BR /><SPAN>[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels and hysteresis; normal drive strength.</SPAN><BR /><SPAN>[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O functions with TTL levels, and hysteresis; high drive strength.</SPAN><BR /><SPAN>4.The P3_2 is “OL” during “Reset state” descripted in UM10430. What are the configurations of I/O pas? I referred to the block diagram of the I/O pad but I can’t figure out the configurations.</SPAN><BR /><SPAN>Please refer to the Fig. 34. Block diagram of the I/O pad of UM10430.</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:27:10 GMT https://community.nxp.com/t5/LPC-Microcontrollers/The-spec-clarifying-for-LPC185x/m-p/540857#M12150 lpcware 2016-06-15T18:27:10Z Re: The spec clarifying for LPC185x. https://community.nxp.com/t5/LPC-Microcontrollers/The-spec-clarifying-for-LPC185x/m-p/540858#M12151 <HTML><HEAD></HEAD><BODY><STRONG>Content originally posted in LPCWare by starblue on Tue Sep 01 05:10:17 MST 2015</STRONG><BR /><SPAN>For electrical characteristics like drive strengths, take a look at the data sheet.</SPAN></BODY></HTML> Wed, 15 Jun 2016 18:27:11 GMT https://community.nxp.com/t5/LPC-Microcontrollers/The-spec-clarifying-for-LPC185x/m-p/540858#M12151 lpcware 2016-06-15T18:27:11Z