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    <title>LPC MicrocontrollersのトピックProblem booting 1857 from SPIFI w/ trivial app</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Problem-booting-1857-from-SPIFI-w-trivial-app/m-p/540677#M12095</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Grant.Edwards on Wed Apr 24 11:56:33 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;P&gt;&lt;BR /&gt;I'm using a Keil mcb1857 board, and I'm unable to get it to boot an&lt;BR /&gt;app from SPIFI either directly, or by adding a header so it gets&lt;BR /&gt;copied into SRAM and run from there.&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The quad SPI part is identified by OpenOCD as a Spansion s25FL032, and&lt;BR /&gt;the Keil schematic shows it as an S25FL032P0XMFI01.&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The application is a trivial assembly-language program that flashes an&lt;BR /&gt;LED.&amp;nbsp; The code is position-independent and is shown below:&lt;BR /&gt;&lt;BR /&gt;&amp;lt;code&amp;gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .thumb&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .syntax unified&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .section .text&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ configure P9_0 as GPIO P4.12&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x40086480&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r1, =0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1, [r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ configure GPIO 4.12 as output&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x400F6010&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r1, =(1&amp;lt;&amp;lt;12)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1, [r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ point to P4 toggle register&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x400F6310&lt;BR /&gt;loop:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ toggle P4.12&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1,[r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ approx 50ms delay when running at 96MHz (ISP mode)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ approx 400ms delay when running at 12MHz (JTAG)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r3, =1000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;delay:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; subs r3, 1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bne&amp;nbsp; delay&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; b loop&lt;BR /&gt;&amp;lt;/code&amp;gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can run the code without problems in a variety of ways:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;When I load the program into SRAM at 0x10000000 using the ISP protocol&lt;BR /&gt;it runs fine.&amp;nbsp; I can then map the SRAM to 0, and run it starting at 0,&lt;BR /&gt;and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;When I enable SDRAM, map SDRAM to 0, load the program at 0, set PC=0&lt;BR /&gt;and go, runs fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can program it into SPIFI, and execute it at 0x14000000 or&lt;BR /&gt;0x80000000 using gdb+openocd+JTAG, and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can map SPIFI to address 0, and execute it at 0, and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;What I can't get to work is actually booting from SPIFI.&amp;nbsp; When I set&lt;BR /&gt;the startup pins to select SPIFI as boot source, I can see some data&lt;BR /&gt;being read from SPIFI. Then SPIFI activity stops, and the board is&lt;BR /&gt;dead.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt; &lt;BR /&gt;If I add a program header to the image in SPIFI, then it reads about&lt;BR /&gt;10X as much data as without the header (it appears to be reading an&lt;BR /&gt;entire 512-byte block as it should), then the board is dead.&amp;nbsp; If I&lt;BR /&gt;increase the block counter in the header from 1 to 2, it reads twice&lt;BR /&gt;again as much data from SPIFI after boot, then the board is dead.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The boot ROM is obviously recognizing the SPIFI part: without an image&lt;BR /&gt;header it only reads a small amount from SPIFI.&amp;nbsp; With an image header,&lt;BR /&gt;the block count in the header controls how much is read.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt; Is there something unique you have to include in the application&lt;BR /&gt;code when it's being _booted_ from SPIFI that isn't required when&lt;BR /&gt;you're running from SPIFI, or SRAM, or SDRAM?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:25:29 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:25:29Z</dc:date>
    <item>
      <title>Problem booting 1857 from SPIFI w/ trivial app</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Problem-booting-1857-from-SPIFI-w-trivial-app/m-p/540677#M12095</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Grant.Edwards on Wed Apr 24 11:56:33 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;P&gt;&lt;BR /&gt;I'm using a Keil mcb1857 board, and I'm unable to get it to boot an&lt;BR /&gt;app from SPIFI either directly, or by adding a header so it gets&lt;BR /&gt;copied into SRAM and run from there.&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The quad SPI part is identified by OpenOCD as a Spansion s25FL032, and&lt;BR /&gt;the Keil schematic shows it as an S25FL032P0XMFI01.&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The application is a trivial assembly-language program that flashes an&lt;BR /&gt;LED.&amp;nbsp; The code is position-independent and is shown below:&lt;BR /&gt;&lt;BR /&gt;&amp;lt;code&amp;gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .thumb&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .syntax unified&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; .section .text&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ configure P9_0 as GPIO P4.12&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x40086480&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r1, =0&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1, [r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ configure GPIO 4.12 as output&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x400F6010&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r1, =(1&amp;lt;&amp;lt;12)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1, [r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ point to P4 toggle register&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r0, =0x400F6310&lt;BR /&gt;loop:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ toggle P4.12&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; str r1,[r0]&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ approx 50ms delay when running at 96MHz (ISP mode)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; @ approx 400ms delay when running at 12MHz (JTAG)&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; ldr r3, =1000000&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &lt;BR /&gt;delay:&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; subs r3, 1&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; bne&amp;nbsp; delay&lt;BR /&gt;&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; b loop&lt;BR /&gt;&amp;lt;/code&amp;gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can run the code without problems in a variety of ways:&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;When I load the program into SRAM at 0x10000000 using the ISP protocol&lt;BR /&gt;it runs fine.&amp;nbsp; I can then map the SRAM to 0, and run it starting at 0,&lt;BR /&gt;and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;When I enable SDRAM, map SDRAM to 0, load the program at 0, set PC=0&lt;BR /&gt;and go, runs fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can program it into SPIFI, and execute it at 0x14000000 or&lt;BR /&gt;0x80000000 using gdb+openocd+JTAG, and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;I can map SPIFI to address 0, and execute it at 0, and it works fine.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;What I can't get to work is actually booting from SPIFI.&amp;nbsp; When I set&lt;BR /&gt;the startup pins to select SPIFI as boot source, I can see some data&lt;BR /&gt;being read from SPIFI. Then SPIFI activity stops, and the board is&lt;BR /&gt;dead.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt; &lt;BR /&gt;If I add a program header to the image in SPIFI, then it reads about&lt;BR /&gt;10X as much data as without the header (it appears to be reading an&lt;BR /&gt;entire 512-byte block as it should), then the board is dead.&amp;nbsp; If I&lt;BR /&gt;increase the block counter in the header from 1 to 2, it reads twice&lt;BR /&gt;again as much data from SPIFI after boot, then the board is dead.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;The boot ROM is obviously recognizing the SPIFI part: without an image&lt;BR /&gt;header it only reads a small amount from SPIFI.&amp;nbsp; With an image header,&lt;BR /&gt;the block count in the header controls how much is read.&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;P&gt; Is there something unique you have to include in the application&lt;BR /&gt;code when it's being _booted_ from SPIFI that isn't required when&lt;BR /&gt;you're running from SPIFI, or SRAM, or SDRAM?&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:25:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Problem-booting-1857-from-SPIFI-w-trivial-app/m-p/540677#M12095</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:25:29Z</dc:date>
    </item>
    <item>
      <title>Re: Problem booting 1857 from SPIFI w/ trivial app</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Problem-booting-1857-from-SPIFI-w-trivial-app/m-p/540678#M12096</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Grant.Edwards on Wed Apr 24 13:04:02 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;P&gt;After more trial and error it appears that the Boot ROM expects the image to have a vector table.&lt;/P&gt;&lt;BR /&gt;&lt;P&gt;Rather than starting execution from 0x80000000 as the user manual states, it appears that it loads the SP from 0x80000000 and PC from 0x80000004, and starts execution from ([0x80000004] &amp;amp;amp; 0xfffffffe).&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:25:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Problem-booting-1857-from-SPIFI-w-trivial-app/m-p/540678#M12096</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:25:30Z</dc:date>
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