LPC MicrocontrollersのトピックRe: LPC1114 SPI 24Mhz CLK spi_receive not work. the code:

LPC1114 SPI 24Mhz CLK spi_receive not work. the code:

lpcware — Wed, 15 Jun 2016 19:39:10 GMT

Content originally posted in LPCWare by sinanjj on Tue Nov 19 00:43:49 MST 2013
void spi_init(void)
{
LPC_SYSCON->PRESETCTRL |= (0x1<<0);//reset de-asserted
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<11);//Enables clock for SPI0
LPC_SYSCON->SSP0CLKDIV = 0x01;// Divided by 1. SSP0CLK=Fmain/1=48Mhz
LPC_IOCON->PIO0_8 &= ~0x07; LPC_IOCON->PIO0_8 |= 0x01;// MISO0
LPC_IOCON->PIO0_9 &= ~0x07; LPC_IOCON->PIO0_9 |= 0x01;// MOSI0
LPC_IOCON->SCK_LOC = 0x00;//Selects SCK0 function in pin location PIO0_10. JTAG DISABLED
LPC_IOCON->JTAG_TCK_PIO0_10 &= ~0x07; LPC_IOCON->JTAG_TCK_PIO0_10 |= 0x02;// SPI CLK0
LPC_IOCON->PIO0_2 &= ~0x07; LPC_IOCON->PIO0_2 |= 0x01;// SPI SSEL0
LPC_SSP0->CR0 = 0x01cf;// data size 16bit, CPOL=1(CLK idle high), CPHA=1, SCR=1
LPC_SSP0->CPSR = 0x2;// SSPCPSR clock prescale register, master mode, minimum divisor is 0x02. Fspi=SPI0CLK/(CPSDVSR*[SCR+1])=48M/(2*(1+1))=12M
LPC_SSP0->CR1 |= (0x1<<1);// Master mode
}
void spi_send(unsigned char *buf, unsigned int count)
{
unsigned int i; unsigned int dummy;
for (i=0; i<count; i++) {
while ((LPC_SSP0->SR & 0x12) != 0x02); LPC_SSP0->DR = *buf;
buf++;
while ((LPC_SSP0->SR & 0x14) != 0x04); dummy = LPC_SSP0->DR;// Whenever a byte is written, MISO FIFO counter increments, Clear FIFO on MISO. Otherwise, when SSP0Receive() is called, previous data byte is left in the FIFO
}
}
unsigned int spi_receive(unsigned char *buf, unsigned int count)
{
uint32_t i;
for (i=0; i<count; i++) {
LPC_SSP0->DR = 0x0;
while ((LPC_SSP0->SR & 0x14) != 0x04);// Wait until the Busy bit is cleared
*buf = LPC_SSP0->DR;
buf++;
}
}

This is the working code.

LPC_SSP0->CR0 = 0x00cf;// data size 16bit, CPOL=1(CLK idle high), CPHA=1, SCR=0

if set SCR=0 to get 24Mhz speed, spi_receive will not work. It get all 0xff.

The logic wave is the same and right.

Re: LPC1114 SPI 24Mhz CLK spi_receive not work. the code:

lpcware — Wed, 15 Jun 2016 19:39:11 GMT

Content originally posted in LPCWare by sinanjj on Wed Nov 27 00:05:32 MST 2013
void spi_init(void)
{
LPC_SYSCON->PRESETCTRL |= (0x1<<0);//reset de-asserted
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<11);//Enables clock for SPI0
LPC_SYSCON->SSP0CLKDIV = 0x01;// Divided by 1. SSP0CLK=Fmain/1=48Mhz
LPC_IOCON->PIO0_8 &= ~0x07; LPC_IOCON->PIO0_8 |= 0x01;// MISO0
LPC_IOCON->PIO0_8 &= ~0x18;
LPC_IOCON->PIO0_9 &= ~0x07; LPC_IOCON->PIO0_9 |= 0x01;// MOSI0
LPC_IOCON->SCK_LOC = 0x00;//Selects SCK0 function in pin location PIO0_10. JTAG DISABLED
LPC_IOCON->JTAG_TCK_PIO0_10 &= ~0x07; LPC_IOCON->JTAG_TCK_PIO0_10 |= 0x02;// SPI CLK0
LPC_IOCON->PIO0_2 &= ~0x07; LPC_IOCON->PIO0_2 |= 0x01;// SPI SSEL0
LPC_SSP0->CR0 = 0x00cf;// data size 16bit, CPOL=1(CLK idle high), CPHA=1, SCR=1
LPC_SSP0->CPSR = 0x2;// SSPCPSR clock prescale register, master mode, minimum divisor is 0x02. Fspi=SPI0CLK/(CPSDVSR*[SCR+1])=48M/(2*(0+1))=24M
LPC_SSP0->CR1 |= (0x1<<1);// Master mode
}

Re: LPC1114 SPI 24Mhz CLK spi_receive not work. the code:

lpcware — Wed, 15 Jun 2016 19:39:11 GMT

Content originally posted in LPCWare by sinanjj on Wed Nov 27 00:07:33 MST 2013
It's a hardware problem.

The code is right.