LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:51 GMT

Content originally posted in LPCWare by namorada on Tue Sep 29 06:59:08 MST 2015
Hi!

I'm facing a problem when interfacing a SRAM to the LPC1825 (part of the schematic attached).

Here is my code:

void RA_InitEmc(u32 u32_Freq)
{
ES_DeclareFonctionGPIOs(1, 7, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3));//D0
ES_DeclareFonctionGPIOs(1, 8, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //D1
ES_DeclareFonctionGPIOs(1, 9, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)); //D2
ES_DeclareFonctionGPIOs(1, 10, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |SCU_MODE_FUNC3)); //D3
ES_DeclareFonctionGPIOs(1, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)); //D4
ES_DeclareFonctionGPIOs(1, 12, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)); //D5
ES_DeclareFonctionGPIOs(1, 13, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)); //D6
ES_DeclareFonctionGPIOs(1, 14, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC3)); //D7
ES_DeclareFonctionGPIOs(1, 15, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC6)); //D8
ES_DeclareFonctionGPIOs(1, 16, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC6)); //D9
ES_DeclareFonctionGPIOs(1, 18, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7)); //D10
ES_DeclareFonctionGPIOs(1, 20, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC7)); //D11
ES_DeclareFonctionGPIOs(5, 0, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //D12
ES_DeclareFonctionGPIOs(5, 1, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //D13
ES_DeclareFonctionGPIOs(5, 2, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //D14
ES_DeclareFonctionGPIOs(5, 3, (SCU_MODE_INACT  | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //D15

ES_DeclareFonctionGPIOs(2, 9, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A0
ES_DeclareFonctionGPIOs(2, 10, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A1
ES_DeclareFonctionGPIOs(2, 11, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A2
ES_DeclareFonctionGPIOs(2, 12, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A3
ES_DeclareFonctionGPIOs(2, 13, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A4
ES_DeclareFonctionGPIOs(1, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //A5
ES_DeclareFonctionGPIOs(1, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //A6
ES_DeclareFonctionGPIOs(1, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A7
ES_DeclareFonctionGPIOs(2, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A8
ES_DeclareFonctionGPIOs(2, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC3)); //A9
ES_DeclareFonctionGPIOs(2, 6, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //A10
ES_DeclareFonctionGPIOs(2, 2, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //A11
ES_DeclareFonctionGPIOs(2, 1, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC2)); //A12
ES_DeclareFonctionGPIOs(2, 0, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |   SCU_MODE_FUNC2)); //A13
ES_DeclareFonctionGPIOs(6, 8, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC1)); //A14
ES_DeclareFonctionGPIOs(6, 7, (SCU_MODE_INACT | SCU_MODE_INBUFF_EN |  SCU_MODE_FUNC1)); //A15

ES_DeclareFonctionGPIOs(6, 6, (SCU_MODE_INACT  |  SCU_MODE_FUNC1)); //nBLS1
ES_DeclareFonctionGPIOs(1, 3, (SCU_MODE_INACT  |  SCU_MODE_FUNC3)); //nOE
ES_DeclareFonctionGPIOs(1, 4, (SCU_MODE_INACT  |  SCU_MODE_FUNC3)); //nBLS0
//ES_DeclareFonctionGPIOs(1, 5, (SCU_MODE_INACT   |  SCU_MODE_FUNC3)); //nCS0
ES_DeclareFonctionGPIOs(6, 3, (SCU_MODE_INACT   |  SCU_MODE_FUNC3)); //nCS1

ES_DeclareFonctionGPIOs(1, 6, (SCU_MODE_INACT   |   SCU_MODE_FUNC3)); //nWE

/********* ACTIVATION HORLOGE ***********/
LPC_CREG->CREG6 &= ~(1 << 16);
LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG |= (0x01);
LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG |= 1<<5;
LPC_CCU1->CLKCCU[CLK_MX_EMC_DIV].CFG |= 1<<1;
LPC_CCU1->CLKCCU[CLK_MX_EMC].CFG |= 1;                           // Activer l'horloge du module EMC
LPC_CCU1->CLKCCU[CLK_MX_EMC].CFG |= 1<<1;
LPC_SCU->EMCDELAYCLK &= 0xFFFF0000;
LPC_EMC->DYNAMICCONTROL &= ~EMC_DYN_CONTROL_ENABLE; // Disable dynamic
LPC_EMC->CONTROL = 0x00000001; // Enable EMC, Normal Memory Map, Normal Mode
LPC_EMC->CONFIG &=  0xFFFFFFFE; // little Endian
LPC_EMC->STATICCONFIG1= EMC_STATIC_CONFIG_MEM_WIDTH_16 | EMC_STATIC_CONFIG_BLS_HIGH | EMC_STATIC_CONFIG_EW_DISABLE; // 16bits, Pas de Write Protect
LPC_EMC->STATICWAITWEN1 = RA_CalculNbCycles(10,u32_Freq,1);  // WAITWEN = 10ns : n + 1 0x0F
LPC_EMC->STATICWAITOEN1 = RA_CalculNbCycles(10,u32_Freq,0);//WAITOEN = 10ns : n
LPC_EMC->STATICWAITRD1 = RA_CalculNbCycles(50,u32_Freq,1);//WAITRD = 50ns : n + 1
LPC_EMC->STATICWAITPAG1 = RA_CalculNbCycles(20,u32_Freq,1);
LPC_EMC->STATICWAITWR1 = RA_CalculNbCycles(45,u32_Freq,2);//WAITWR = 40ns : n + 2  0x1F
LPC_EMC->STATICWAITTURN1 = 0;   //WAITWR = 20ns
LPC_EMC->STATICEXTENDEDWAIT = 10;//0x1CC;
}

I'm testing the SRAM with this function:

u8 RA_TestRam(void)
{
u16 *pu16_RamPtr;
u32 i;
u32 u32_NbErreur;
u16 u16_Valeur;
u32_NbErreur = 0;
pu16_RamPtr = (u16 *)RAM_BASE_ADDRESS;

// efface la mémoire à 0
for(i=0; i<(RAM_TAILLE/2); i++)
{
*pu16_RamPtr = 0;
pu16_RamPtr++;
}
pu16_RamPtr = (u16 *)RAM_BASE_ADDRESS;
for(i=0; i<(RAM_TAILLE/2); i++)
{
*pu16_RamPtr = (u16)i;
pu16_RamPtr++;
}
// lecture des valeurs
pu16_RamPtr = (u16 *)RAM_BASE_ADDRESS;
for(i=0; i<(RAM_TAILLE/2); i++)
{
u16_Valeur = 0;
u16_Valeur = *pu16_RamPtr;
pu16_RamPtr++;
if(u16_Valeur != (u16)i)
{
  u32_NbErreur++;
}
}

// efface la mémoire à 0
pu16_RamPtr = (u16 *)RAM_BASE_ADDRESS;
for(i=0; i<(RAM_TAILLE/2); i++)
{
*pu16_RamPtr++ = 0;
}

if(u32_NbErreur)
return(1);
else
return(0);
}

The main problem is that if i look in the memory at 0x1d000000 (breakpoint on

Quote:
*pu16_RamPtr = (u16)i;

, i see that the LPC1825 write at two sector (picture attached).
I don't know why the LPC1825 write there... Any idea of what i'm missing?

Thanks.

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:53 GMT

Content originally posted in LPCWare by mc on Tue Sep 29 19:06:01 MST 2015
Hi namorada,
I was unable to download schematic. Could you please post it again?

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:53 GMT

Content originally posted in LPCWare by namorada on Tue Sep 29 23:51:14 MST 2015
Hi,

I don't know why it is not working. I just repost the schematic here, on the forum.
I also uploaded it here : schematic.

Does it work for you now?

Thanks.

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:54 GMT

Content originally posted in LPCWare by MikeSimmonds on Wed Sep 30 17:09:23 MST 2015
Maybe the forum does not like the plus (+) in the upload filename?

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:54 GMT

Content originally posted in LPCWare by bavarian on Tue Oct 06 05:19:21 MST 2015
You use CS0 and this is the address range starting at 0x1C00 0000.
What you see on 0x1D00 0000 are phantom values.

The schematic is fine, I also don't see a problem in the init code (only had a quick look).

Regards,
NXP Support Team

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:55 GMT

Content originally posted in LPCWare by namorada on Tue Oct 06 06:49:29 MST 2015
Hi,

I'm not using CS0, but CS1 (using 0x1D00 0000 as defined in UM10430 page 488 of 1264).

I have defined the space :

#define RAM_BASE_ADDRESS       0x1d000000
#define RAM_TAILLE             0x20000     // 128ko

And, in the project, see the attached pic.

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:56 GMT

Content originally posted in LPCWare by namorada on Tue Oct 06 08:06:38 MST 2015
Is there an evaluation kit incorporating a lpc1825 and a SRAM? This will allow me to test my software on a validated hardware and compare it with someone who have it ...

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:56 GMT

Content originally posted in LPCWare by namorada on Thu Oct 08 00:45:11 MST 2015
Sorry, i misunderstood your comment.
Indeed, in my schematics, i'm using CS0. Since it don't work, i also tried using CS1 (it is why in my source code there is 0x1D00 0000).
So, my schematics is not uptodate.

Nevermind, since it don't work (same result with CS1), i returned to CS0 (soft and hard).

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:57 GMT

Content originally posted in LPCWare by bavarian on Wed Oct 14 06:33:03 MST 2015
The Hitex board with the LPC1857 has a 16-bit SRAM on board, so I will give it a try.

Regards,
NXP Support Team.

Re: LPC1825 and external SRAM

lpcware — Wed, 15 Jun 2016 18:21:58 GMT

Content originally posted in LPCWare by DF9DQ on Wed Oct 14 07:48:31 MST 2015
In the code you've posted you select function 3 for P1_2, but EMC_A7 is function 2.
Could this be the problem?

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