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    <title>LPC Microcontrollers中的主题 Is this SDRAM compatible with 18xx ?</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Is-this-SDRAM-compatible-with-18xx/m-p/536242#M11155</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by chris.bayley on Thu Jun 18 18:35:16 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I am working with a form factor preproduction prototype PCB fitted with an LPC1837 and an ISSI SDRAM (IS42SM16200D) which is a 1M x 16bit x 2banks device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;From it's data sheet:&lt;/SPAN&gt;&lt;BR /&gt;&lt;I&gt;In general, this 32Mb SDRAM (1M x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 512 columns by 16-bits&lt;BR /&gt;&lt;/I&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am becoming increasingly concerned that the EMC addressing modes of the 18xx may not support the Row/Column layout of this device:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From Table 365 of UM10430:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;[img]&lt;/SPAN&gt;&lt;A _jive_internal="true" class="" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fsystem%2Ffiles%2Fimages%2FScreen%2520Shot%25202015-06-19%2520at%25201.10.46%2520pm.png%5B%2Fimg%5D"&gt;http://www.lpcware.com/system/files/images/Screen%20Shot%202015-06-19%20at%201.10.46%20pm.png[/img]&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So my SDRAM is 32Mb (1M x 16 x 2) and according to its data sheet it is laid out as:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2048 rows x 512 columns x 2 banks x 16bit&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;hence the row addressing is on A0-A10 and the col on A0-A8.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I cannot see any address mapping mode in Table 365 that indicates support for this configuration, are we up a creek or is there some mapping that will yield full access to the memory ???&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried all the given options support 2 banks but have not established a usable result.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Cheers all,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chris &lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:22:27 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:22:27Z</dc:date>
    <item>
      <title>Is this SDRAM compatible with 18xx ?</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Is-this-SDRAM-compatible-with-18xx/m-p/536242#M11155</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by chris.bayley on Thu Jun 18 18:35:16 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I am working with a form factor preproduction prototype PCB fitted with an LPC1837 and an ISSI SDRAM (IS42SM16200D) which is a 1M x 16bit x 2banks device.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;From it's data sheet:&lt;/SPAN&gt;&lt;BR /&gt;&lt;I&gt;In general, this 32Mb SDRAM (1M x 16Bits x 2banks) is a dual-bank DRAM that operates at 3.0V/3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 512 columns by 16-bits&lt;BR /&gt;&lt;/I&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am becoming increasingly concerned that the EMC addressing modes of the 18xx may not support the Row/Column layout of this device:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;From Table 365 of UM10430:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;SPAN&gt;[img]&lt;/SPAN&gt;&lt;A _jive_internal="true" class="" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fsystem%2Ffiles%2Fimages%2FScreen%2520Shot%25202015-06-19%2520at%25201.10.46%2520pm.png%5B%2Fimg%5D"&gt;http://www.lpcware.com/system/files/images/Screen%20Shot%202015-06-19%20at%201.10.46%20pm.png[/img]&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;So my SDRAM is 32Mb (1M x 16 x 2) and according to its data sheet it is laid out as:&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;2048 rows x 512 columns x 2 banks x 16bit&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;hence the row addressing is on A0-A10 and the col on A0-A8.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I cannot see any address mapping mode in Table 365 that indicates support for this configuration, are we up a creek or is there some mapping that will yield full access to the memory ???&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have tried all the given options support 2 banks but have not established a usable result.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Cheers all,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chris &lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:22:27 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Is-this-SDRAM-compatible-with-18xx/m-p/536242#M11155</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:22:27Z</dc:date>
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