USB payload

lpcware — Wed, 15 Jun 2016 18:19:59 GMT

Content originally posted in LPCWare by decai.wang@carestream.com on Tue Mar 20 22:34:42 MST 2012
Hi,Sir!

Can you give some detailed information about the payload of LPC18XX USB as slave device? I want to upgrade LPC1768 by LPC18xx. because the usb speed of LPC18xx can support high speed mode(480M).

it is better if BULK mode is compared with LPC1768 and LPC18xx.

Thank very much!

Re: USB payload

lpcware — Wed, 15 Jun 2016 18:20:00 GMT

Content originally posted in LPCWare by tranquang.nguyen on Thu Mar 22 20:43:43 MST 2012
Hi, Decai.Wang,

With LPC17xx, I see that a RAM based FIFO (EndPoint RAM) is used for each endpoint buffer; for transferring data, we just use the Transmit/Receive Registers to read or write data.
But in LPC18xx, with high-speed USB support, a new device data structure is defined: each endpoint direction has a linked list of transfer tasks with dQH (device queue head) and dTD (device transfer descriptor) (pls see section 21.9 and 21.10 in UM10430 for more details).
LPC18xx use "ENDPOINTLISTADDR" register to point to an area of memory that contains a group of all dQHs in a sequential list (see Fig.48/page 534 in UM10430).
To transmit/receive data, we have to "prime endpoint"(by setting the corresponding bit in ENDPTPRIME register - see UM10430) after filling out the device data structure (dQH and dTD).
Besides, LPC1850/30/20 has USB ROM Driver in the boot ROM, implements CDC, HID, MSC device class (see chapter 23 - UM10430)
You can follow the link below (LPC1800CMSIS) for some USB, USB ROM examples (update regularly)
http://sw.lpcware.com/index.php?p=lpc18xx.git&a=summary
UM10430 Link:
http://lpcware.com/content/nxpfile/lpc18xx-user-manual
Hope this helps you, Decai.Wang

Regards,
Quang

Re: USB payload

lpcware — Wed, 15 Jun 2016 18:20:01 GMT

Content originally posted in LPCWare by decai.wang@carestream.com on Sun Mar 25 21:19:47 MST 2012
Thanks for your reply!

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