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    <title>topic LPC1112FHN33/102 Pin Mux Fail on PIO0_10 / SWCLK in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532510#M10428</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by clkunde on Tue Dec 03 05:08:18 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Dear members,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPCXpresso and LPCOPEN 2.0 to develop a new firmware for the LPC1112FHN33/102 IC.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I verified after many tests that the PIN 19 (SWCLK/GPIO0_10/SCK0/CT16B0_MAT2) don't change the function from SWCLK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the board_sysinit.c I inserted the line in the Pin Mux table:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;{(uint32_t) IOCON_PIO0_10, IOCON_FUNC1}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;If I comment or uncomment this line, the effect is the same: the chip don't switch to GPIO function. It is always fixed to the SWCLK Jtag function.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The same don't happen with Pin 25 (SWDIO/PIO1_3). If I change to GPIO function this works appropriately.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;What should I do? Somebody had the same problem?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Claudio Kunde&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 19:35:49 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T19:35:49Z</dc:date>
    <item>
      <title>LPC1112FHN33/102 Pin Mux Fail on PIO0_10 / SWCLK</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532510#M10428</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by clkunde on Tue Dec 03 05:08:18 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Dear members,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm using LPCXpresso and LPCOPEN 2.0 to develop a new firmware for the LPC1112FHN33/102 IC.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I verified after many tests that the PIN 19 (SWCLK/GPIO0_10/SCK0/CT16B0_MAT2) don't change the function from SWCLK.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In the board_sysinit.c I inserted the line in the Pin Mux table:&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;{(uint32_t) IOCON_PIO0_10, IOCON_FUNC1}&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;If I comment or uncomment this line, the effect is the same: the chip don't switch to GPIO function. It is always fixed to the SWCLK Jtag function.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The same don't happen with Pin 25 (SWDIO/PIO1_3). If I change to GPIO function this works appropriately.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;What should I do? Somebody had the same problem?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you!&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Claudio Kunde&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:35:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532510#M10428</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:35:49Z</dc:date>
    </item>
    <item>
      <title>Re: LPC1112FHN33/102 Pin Mux Fail on PIO0_10 / SWCLK</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532511#M10429</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by clkunde on Mon Dec 09 11:41:35 MST 2013&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;There is an error in iocon_11xx.h file.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The IOCON_PIO0_10 memory map was declared as 0x070.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;The correct memory address offset is 0x068, according datasheet.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm very frustrated with the LPCOpen. My first project and I found several mistakes on framework...&lt;/SPAN&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:35:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532511#M10429</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:35:50Z</dc:date>
    </item>
    <item>
      <title>Re: LPC1112FHN33/102 Pin Mux Fail on PIO0_10 / SWCLK</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532512#M10430</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by nerd herd on Thu Feb 19 14:00:27 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi clkunde,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Thank you for reporting the solution. This will be investigated and reported to the software team.&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 19:35:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1112FHN33-102-Pin-Mux-Fail-on-PIO0-10-SWCLK/m-p/532512#M10430</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T19:35:51Z</dc:date>
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