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    <title>LPC Microcontrollers中的主题 Re: LPC1857 C_CAN0 Interrupt problem</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532146#M10355</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Fri Apr 17 11:40:54 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;hi, Thanks for pointing out the issue in the UM. We will correct it.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;For your development benefit, can you use the LPCOpen example periph_ccan example for a try?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fnxpfile%2Flpcopen-software-development-platform-lpc18xx-packages-0" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:19:40 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:19:40Z</dc:date>
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      <title>LPC1857 C_CAN0 Interrupt problem</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532144#M10353</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by Yannick.C on Tue Feb 24 05:26:54 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Dear All,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;When an interruption is triggered on C_CAN0 the program go to Hardfault handler. If I disable interrupts of the C_CAN0, it seems to work correctly.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;If I change controller to C_CAN1, interrupt occurs without any troubles.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;In UM10430 rev2.6 I think there is an error on Table 72 (NVIC interrupt sources). All vector offset are wrong (and overlap with previous) from the interrupt ID 37 (GPIO pin interrupt 5). I think offset for C_CAN0 is 0x10C instead of 0xFC. But the default startup.s do not have this problem so it's just a datasheet error.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;I think the real problem is that C_CAN0 handler address is read from address 0x0C instead of 0x10C, 0x0C is the offset of Hardfault.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I have a LPC1857JET256 with a -Y revision (normally engeineering sample of the Rev A).&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I really need to use interrupt and C_CAN0, is someone has encountered the same problem ?&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Yannick&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:19:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532144#M10353</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:19:38Z</dc:date>
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    <item>
      <title>Re: LPC1857 C_CAN0 Interrupt problem</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532145#M10354</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by SteveO on Wed Apr 15 17:21:39 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;I'm not using CAN0, so I can't answer your question.&amp;nbsp; I agree that all the vector offsets above PIN_INT4 in Table 73 appear to be wrong.&amp;nbsp; 0x10c appears to be what was intended for C_CAN0.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Hardfault usually occurs when your ISR reads or writes an invalid address, like when a pointer is not initialized. However, that doesn't explain why CAN1 works.&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;ETA: Check Errata sheet item 3.1&amp;nbsp; "Writes to CAN registers write through to other peripherals"&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:19:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532145#M10354</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:19:39Z</dc:date>
    </item>
    <item>
      <title>Re: LPC1857 C_CAN0 Interrupt problem</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532146#M10355</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Fri Apr 17 11:40:54 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;hi, Thanks for pointing out the issue in the UM. We will correct it.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;For your development benefit, can you use the LPCOpen example periph_ccan example for a try?&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fnxpfile%2Flpcopen-software-development-platform-lpc18xx-packages-0" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;regards,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:19:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/LPC1857-C-CAN0-Interrupt-problem/m-p/532146#M10355</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:19:40Z</dc:date>
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