LPC11 - interrupts during IAP

lpcware — Wed, 15 Jun 2016 19:31:41 GMT

Content originally posted in LPCWare by push2eject on Tue Jul 28 18:42:39 MST 2015
A heads up: It seems interrupts must be disabled for all IAP calls, not just erase/write calls.

From the LPC11C14 user manual (my highlight):

20.4.7 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a [color=#f00]flash erase/write IAP
call.[/color] The IAP code does not use or disable interrupts.

I took this to mean I only had to disable interrupts when performing an erase or write comman. However, I found that the PC was occasionally jumping to 0xfffffffe unless I also disabled interrupts during "Prepare Sectors For Write Operation" and "Compare" IAP calls as well. Took some while to figure this out, as it was a very intermittent fault.

#NotObviousToMe

Kevin.

Re: LPC11 - interrupts during IAP

lpcware — Wed, 15 Jun 2016 19:31:42 GMT

Content originally posted in LPCWare by nerd herd on Wed Jul 29 07:34:00 MST 2015
Hi push2eject,

I will review this and talk to the documentation team about making this less ambiguous. Thank you for your feedback.

topic Re: LPC11 - interrupts during IAP in LPC Microcontrollers

LPC11 - interrupts during IAP

Re: LPC11 - interrupts during IAP