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    <title>topic Re: Ethernet DMA not receiving RX packets from Ethernet PHY chip in LPC Microcontrollers</title>
    <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-DMA-not-receiving-RX-packets-from-Ethernet-PHY-chip/m-p/530950#M10104</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Tue Apr 28 19:49:54 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;You could bring up the Ethernet example in the LPCOpen package and compare the setup sequence and register setting with your code. Setup the oscilloscope to see if all the physical signals are as expected as well...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fnxpfile%2Flpcopen-software-development-platform-lpc18xx-packages-0" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards!&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Jun 2016 18:18:41 GMT</pubDate>
    <dc:creator>lpcware</dc:creator>
    <dc:date>2016-06-15T18:18:41Z</dc:date>
    <item>
      <title>Ethernet DMA not receiving RX packets from Ethernet PHY chip</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-DMA-not-receiving-RX-packets-from-Ethernet-PHY-chip/m-p/530949#M10103</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by ashgupta28 on Wed Feb 18 01:53:35 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hello,&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;I am using custom board with LPC18xx with Micrel KSZ8873. I had configured ethernet switch port 3 as RMII with LPC18xx. I am also getting RX data packets on Oscilloscope at RMII RXD lines but these packets are not visible on DMA RX buffer.&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;These are the ethernet settings i am doing:-&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;Chip_ENET_RMIIEnable(LPC_ETHERNET);&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;STRONG&gt;Chip_Clock_EnableOpts(CLK_MX_ETHERNET, true, true, 1);&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;reset(pENET);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Setup MII link divider to /102 and PHY address 1 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;//Chip_ENET_SetupMII(pENET,div, 1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Enhanced descriptors, burst length = 1 */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;DMA_BUS_MODE = DMA_BM_ATDS | DMA_BM_PBL(1) | DMA_BM_RPBL(1);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Initial MAC configuration for checksum offload, full duplex,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; 100Mbps, disable receive own in half duplex, inter-frame gap&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; of 64-bits */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;MAC_CONFIG = MAC_CFG_BL(0) | MAC_CFG_IPC | MAC_CFG_DM |&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;MAC_CFG_DO | MAC_CFG_FES | MAC_CFG_PS | MAC_CFG_IFG(3);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Setup default filter */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;MAC_FRAME_FILTER = MAC_FF_PR | MAC_FF_RA ;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Flush transmit FIFO */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;DMA_OP_MODE = DMA_OM_FTF;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Setup DMA to flush receive FIFOs at 32 bytes, service TX FIFOs at&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; 64 bytes */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;DMA_OP_MODE |= DMA_OM_RTC(1) | DMA_OM_TTC(0);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Clear all MAC interrupts */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;DMA_STAT = DMA_ST_ALL;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Enable MAC interrupts */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;pENET-&amp;gt;DMA_INT_EN = 0;/* Enable MAC interrupts */&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Board_ENET_GetMacADDR(macaddr);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;Chip_ENET_SetADDR(LPC_ETHERNET, macaddr);&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Setup descriptors */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;InitDescriptors(TXDescs, ENET_NUM_TX_DESC, RXDescs, ENET_NUM_RX_DESC);&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;/* Attach a buffer to a RX descriptor and queue it for receive */&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;i = 0;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;while (i &amp;lt; ENET_NUM_RX_DESC) {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;ENET_RXQueue(RXBuffer&lt;/SPAN&gt;&lt;I&gt;, EMAC_ETH_MAX_FLEN);&lt;BR /&gt;i++;&lt;BR /&gt;}&lt;BR /&gt;static_txNextIndex = 0;&lt;BR /&gt;Chip_ENET_RXStart(LPC_ETHERNET);&lt;BR /&gt;/* Enable RX/TX after descriptors are setup */&lt;BR /&gt;Chip_ENET_TXEnable(LPC_ETHERNET);&lt;BR /&gt;Chip_ENET_RXEnable(LPC_ETHERNET);&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;/* Check for receive packets */&lt;BR /&gt;&lt;STRONG&gt;workbuff = ENET_RXGet(&amp;amp;rxBytes); Here Inside, code is NOT going inside the loop :-&lt;BR /&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; if ((rxAvail &amp;lt; rxNumDescs) &amp;amp;&amp;amp; (!(RXDescs[rxGet].STATUS &amp;amp; RDES_OWN))) {&lt;/STRONG&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;Please suggest some settings that i have missed out.&lt;BR /&gt;Ashish Gupta&lt;BR /&gt;&lt;BR /&gt;Please suggest what settings i have missed out.&lt;/I&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:18:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-DMA-not-receiving-RX-packets-from-Ethernet-PHY-chip/m-p/530949#M10103</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:18:39Z</dc:date>
    </item>
    <item>
      <title>Re: Ethernet DMA not receiving RX packets from Ethernet PHY chip</title>
      <link>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-DMA-not-receiving-RX-packets-from-Ethernet-PHY-chip/m-p/530950#M10104</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;STRONG&gt;Content originally posted in LPCWare by xianghuiwang on Tue Apr 28 19:49:54 MST 2015&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;Hi, &lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;You could bring up the Ethernet example in the LPCOpen package and compare the setup sequence and register setting with your code. Setup the oscilloscope to see if all the physical signals are as expected as well...&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.lpcware.com%2Fcontent%2Fnxpfile%2Flpcopen-software-development-platform-lpc18xx-packages-0" rel="nofollow" target="_blank"&gt;http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0&lt;/A&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;Regards!&lt;/SPAN&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Jun 2016 18:18:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/LPC-Microcontrollers/Ethernet-DMA-not-receiving-RX-packets-from-Ethernet-PHY-chip/m-p/530950#M10104</guid>
      <dc:creator>lpcware</dc:creator>
      <dc:date>2016-06-15T18:18:41Z</dc:date>
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