topic Re: ADC on Kinetis K20 problem of 7 count step in Kinetis Software Development Kit

ADC on Kinetis K20 problem of 7 count step

holyhope — Thu, 02 Apr 2015 08:37:54 GMT

GoodMorning to all,

I'm developing on K20 with KDS 2.0.0 and KSDK 1.1.0

I do many test...I try the 12 and 16 bit mode , with and without continuous mode, with and without internal averaging (for disabling I need to use the HAL because PEx config and PEx high-level have not routine for disable it)

I use the Dithering with about 200mV of amplitude (that is about 50 count on 12 bit).

I use a custom HW for acquire one value of resistence.

I have a problem: I found some problem of not linarity and a "step" of about 7 count on 12 bit (cross the 1024 bit = 2^10 maybe is the crossing of new bit) that is very clarity enabling dithering!

other this problem I found a very not stable acquired value on 12 bit,.

I Calibrate my HW each time (both the ADC internal calibrating and our external HW for translate count to ohm)

And another big problem is that we have not a similar error in all point of the count range but a very strange and variable error!

We use all double for math calc during averaging

On 16 bit with dithering we have a different behaviour: all work right and we have a very stable value and small error.

There are know problem with K20 internal ADC?

there is something that I can do?

This graph shows the variable error of count and ohm between the count / ohm acquired by ADC and the count / ohm extimated with interpolation

I do not have a constant error so a new calibration can't resolve it

Screenshot 1:

http://postimg.org/image/ujwwj7shh

error ( in ohm) using 12 bit (blue) and 16 bit (red).

I do many many many of this graph in different acquisition of 16 bit and different acquisition of 12 bit with different confguration-.

the result is the same: 12 bit is very very very big AND not constant!

You can see the RED error (16 bit) that is a clarity NOT-LINEARITY-ERRO and is above zero before "4" (that are 800ohm, the first calibration point) and belove zero until "11" (that are 1500 ohm, the second calibration point) after that return positive.

the 12 bit error is very big and haven't a typical distribuition.

(the value of 12 bit are an average of acquire)

Screenshot 2:

View image: Screen Hunter 30 Apr 02 09 26

different try of 12 bit configuration: the error remain the same with the same strange shape of error

Screenshot 3:

View image: Screen Hunter 31 Apr 02 09 27

this graph shows 600 puntual count that are averaged in a 600msec period for calculate a correct value to use.
As you can see the dither moves the count acquired: averaging tham I can have a more precise value.
but... as you can see...there is a step crossing 1024 bit

Screenshot 4

http://postimg.org/image/yldzovks5

another graph of dithering with step

Screenshot 5

View image: Screen Hunter 33 Apr 02 09 32

the same graph but crossin another count value: there is no step!

Screenshot 6

View image: Screen Hunter 34 Apr 02 09 32

One of the PEx configuration ( i try many combination of them)

Screenshot 7
http://postimg.org/image/f637vrrhx

Screenshot 8

View image: Screen Hunter 36 Apr 02 09 34

Many Thanks,

Massimiliano

Edit: modify link to photo

Re: ADC on Kinetis K20 problem of 7 count step

xiangjun_rong — Thu, 09 Apr 2015 09:10:18 GMT

Hi, Massimiliano,

I am sorry for the delay.

Regarding your question, you impress an analog signal to ADC input channel, you add 200mV voltage based on last test every times, in this way, you hope that the ADC digital sample is also linear. For 12 bits resolution ADC, I suppose the Vrefh=VDDA=3.3V, in the case, the voltage resolution(LSB voltage) will be 3.3V/(2**12)=3.3V/4096=0.806mV, the count will be 200mV/0.806mV=248. so after each measurement, the ADC sample should be 248, 496, 744,992...

But you said that the "a "step" of about 7 count on 12 bit", the count should be 248 rather than 7. Maybe I misunderstand you, pls explain.

you add 200mV every times, actually, you are testing DNL(differential non-linearity) spec of the ADC, pls refer to section 6.6.1.2 16-bit ADC electrical characteristics in data sheet of K20, in 12 b its mode, the typical value of DNL is 0.7, the maximum value is -1.1LSB to 1.9LSB, It means that if the last digital sample is for example 260, after you add 200mV, the digital sample should range from (260+248-1) to (260+248+2). Note that the INL is from -2.7 to 1.9 in 12 bits mode.

For your issue of non-linearity, I suppose you use waveform generator to generate 200mV DC voltage to the ADC channel, it has issue, pls note that the reading of digital waveform generator is not precious, I suggest you use a DC meter to test the voltage from waveform generator so that you can generate accurate 200mV incremental voltage.

Hope it can help you.

XiangJun Rong

Re: ADC on Kinetis K20 problem of 7 count step

holyhope — Fri, 10 Apr 2015 08:14:40 GMT

Hi XiangJun Rong

First of all thanks for your answer and no problem for delay!

Maybe, in my description, I have no center the core-question.

I use a dithering and you can see in my graph, I told this information because the problem is more evident in this way but, maybe, we have centred the question near the dithering and my 200mV!

The core-question is this: There is a problem near "1024 " value and neat "2048" value? Near this two value I see a problem of "Missing code" because there is a step of about 7/8 count (in 12 bit mode).

The problem is still present in 16 bit mode

We try with KSDK-DEMO: DAC_ADC_DEMO with FRDM-K64 board and the problem is the same...

so forget, for 1 moment, the dithering. I explain it, because is more evident, but the problem is the missing code!

is a "know problem" of uP FreeScale? Or there is something that I can do?

(Another info: in other range I can see ALL the value of adc without step, se there is no problem about 200mV or dithering etc...)

Many Thanks,

Massimiliano

Re: ADC on Kinetis K20 problem of 7 count step

xiangjun_rong — Mon, 13 Apr 2015 03:58:36 GMT

Hi, Massimiliano,

Now, I see that your problem is the "missing code" of the ADC converter, it means that some digital ADC sample can not be generated, can you list the missing code pattern so that I can report to design/test team for confirmation?

I have checked the errata of K20, the missing code issue of ADC is not mentioned.

BTW, I can not access some of the url you linked in the community.

XiangJun Rong

Re: ADC on Kinetis K20 problem of 7 count step

holyhope — Wed, 15 Apr 2015 12:29:46 GMT

Hi,

thanks for your answer

For see the photo linked you can click on the first link of each couple (the second is a try for use direct forum image posting, but not work). BTW i will change my first topic for remouve the wrong link

The missing code, using 12 bit, are from 1017-1018 to 1024.

Thanks,

Massimiliano

Re: ADC on Kinetis K20 problem of 7 count step

niku — Mon, 16 Jul 2018 10:35:53 GMT

Hi Massimiliano and xiangjun.rong,

I know it's an old issue, but I'm having a very similar problem and I cannot figure out how you solved it.

My case:

- KDSK v1.3.0. ADC0 in K22 with 2 input pins. 16 bits

- ADC0_DP0 is sampled properly

- ADC0_DM0 reports samples with steps, being non-linear. Steps seem to be equidistant and for same distance.

In your lasts comment, you speak about "missing code" in a errata...

- Could you please point me were can I find documentation of this errata?

- Could you please tell me which missing code lines you add to solve this issue?

Thank you in advance.