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    <title>topic Re: How to use freescale k64f  flexbus ? in Kinetis Software Development Kit</title>
    <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635526#M6818</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, ZhaiLing,&lt;/P&gt;&lt;P&gt;As you said that we have not the example code for FlexBus. The FlexBus configuration is only dependent on your hardware connection, for example, the port size, wait state, byte-lane shift, multiplexed or non-multiplexed mode...&lt;/P&gt;&lt;P&gt;Anyway, the flexbusConfig structure corresponds to the FlexBus register contents, pls refer to the Chapter 31&lt;BR /&gt;External Bus Interface (FlexBus) in RM of K64, especially register setting.&lt;/P&gt;&lt;P&gt;After the FlexBus register setting, you can use a pointer to access the external memory, which locates in the FlexBus memory space, pls refer to Chapter 4 Memory Map.&lt;/P&gt;&lt;P&gt;If you still have question, pls tell us the hardware connection so that we can determine the flexbus register setting.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 27 Feb 2017 04:04:29 GMT</pubDate>
    <dc:creator>xiangjun_rong</dc:creator>
    <dc:date>2017-02-27T04:04:29Z</dc:date>
    <item>
      <title>How to use freescale k64f  flexbus ?</title>
      <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635525#M6817</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; Now I want to use flexbus to config the fpga; i can't find design demo of flexbus;only the driver&amp;nbsp;&lt;/P&gt;&lt;P&gt;flexbus_config_t flexbusConfig;&lt;BR /&gt; FLEXBUS_GetDefaultConfig(&amp;amp;flexbusConfig);&lt;BR /&gt; flexbusConfig.waitStates = 2U;&lt;BR /&gt; flexbusConfig.chipBaseAddress = 0x60000000U;&lt;BR /&gt; flexbusConfig.chipBaseAddressMask = 7U;&lt;BR /&gt; FLEXBUS_Init(FB, &amp;amp;flexbusConfig);&lt;/P&gt;&lt;P&gt;I &amp;nbsp;use the demo config the flexbus;but i can't measure&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Feb 2017 05:03:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635525#M6817</guid>
      <dc:creator>zhailing</dc:creator>
      <dc:date>2017-02-15T05:03:08Z</dc:date>
    </item>
    <item>
      <title>Re: How to use freescale k64f  flexbus ?</title>
      <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635526#M6818</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, ZhaiLing,&lt;/P&gt;&lt;P&gt;As you said that we have not the example code for FlexBus. The FlexBus configuration is only dependent on your hardware connection, for example, the port size, wait state, byte-lane shift, multiplexed or non-multiplexed mode...&lt;/P&gt;&lt;P&gt;Anyway, the flexbusConfig structure corresponds to the FlexBus register contents, pls refer to the Chapter 31&lt;BR /&gt;External Bus Interface (FlexBus) in RM of K64, especially register setting.&lt;/P&gt;&lt;P&gt;After the FlexBus register setting, you can use a pointer to access the external memory, which locates in the FlexBus memory space, pls refer to Chapter 4 Memory Map.&lt;/P&gt;&lt;P&gt;If you still have question, pls tell us the hardware connection so that we can determine the flexbus register setting.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Feb 2017 04:04:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635526#M6818</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2017-02-27T04:04:29Z</dc:date>
    </item>
    <item>
      <title>Re: How to use freescale k64f  flexbus ?</title>
      <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635527#M6819</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hi，xiangjun.rong&lt;/P&gt;&lt;P&gt;&amp;nbsp; I read the date from the fpga；the flexbus &amp;nbsp;address is 0x8003，the date is 0x77.&lt;/P&gt;&lt;P&gt;But i read the date is 0x17.I don't kown&amp;nbsp;why ? where is the 0x17 come from? &amp;nbsp;&lt;/P&gt;&lt;P&gt;The _51RDLVT is FB_OE.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/14121i1FA2D8CB341375AE/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;Thanks and best regards&lt;/P&gt;&lt;P&gt;zhai&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Feb 2017 06:20:49 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635527#M6819</guid>
      <dc:creator>zhailing</dc:creator>
      <dc:date>2017-02-27T06:20:49Z</dc:date>
    </item>
    <item>
      <title>Re: How to use freescale k64f  flexbus ?</title>
      <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635528#M6820</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi, ZhaiLing,&lt;/P&gt;&lt;P&gt;Does the timing is from logic analyzer or tools of FPGA, I think it is possible that the data become from 0x77 to 0x17, when&amp;nbsp; the FB_OE becomes high, which means that the FPGA do not drive the data bus, in other words, the data bus is float when&amp;nbsp; the FB_OE becomes high.&lt;/P&gt;&lt;P&gt;BR&lt;/P&gt;&lt;P&gt;Xiangjun Rong&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Feb 2017 07:39:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635528#M6820</guid>
      <dc:creator>xiangjun_rong</dc:creator>
      <dc:date>2017-02-27T07:39:51Z</dc:date>
    </item>
    <item>
      <title>Re: How to use freescale k64f  flexbus ?</title>
      <link>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635529#M6821</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi xiangjun.rong&lt;/P&gt;&lt;P&gt;&amp;nbsp; Yes,I grab the signal with the signaltap ii； The date of &amp;nbsp;fpga send is always 0x77；when &amp;nbsp;the FB_OE becomes high ,the date shoud be 0x77;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/13979i0ABBE92E31E90488/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;my configrations&lt;/P&gt;&lt;P&gt;void FLEXBUS_GetDefaultConfig(flexbus_config_t *config)&lt;BR /&gt;{&lt;BR /&gt; config-&amp;gt;chip = 0; /* Chip 0 FlexBus for validation */&lt;BR /&gt; config-&amp;gt;writeProtect = 0; /* Write accesses are allowed */&lt;BR /&gt; config-&amp;gt;burstWrite = 0; /* Burst-Write disable */&lt;BR /&gt; config-&amp;gt;burstRead = 0; /* Burst-Read disable */&lt;BR /&gt; config-&amp;gt;byteEnableMode = 0; /* Byte-Enable mode is asserted for data write only */&lt;BR /&gt; config-&amp;gt;autoAcknowledge = true; /* Auto-Acknowledge enable */&lt;BR /&gt; config-&amp;gt;extendTransferAddress = 0; /* Extend transfer start/extend address latch disable */&lt;BR /&gt; config-&amp;gt;secondaryWaitStates = 0; /* Secondary wait state disable */&lt;BR /&gt; config-&amp;gt;byteLaneShift =kFLEXBUS_Shifted;//kFLEXBUS_NotShifted; /* Byte-Lane shift disable */&lt;BR /&gt; config-&amp;gt;writeAddressHold = kFLEXBUS_Hold1Cycle; /* Write address hold 1 cycles */&lt;BR /&gt; config-&amp;gt;readAddressHold = kFLEXBUS_Hold2Or1Cycles; /* Read address hold 0 cycles */&lt;BR /&gt; config-&amp;gt;addressSetup =&lt;BR /&gt; kFLEXBUS_FirstRisingEdge; /* Assert ~FB_CSn on the first rising clock edge after the address is asserted */&lt;BR /&gt; config-&amp;gt;portSize = kFLEXBUS_1Byte; /* 1 byte port size of transfer */&lt;BR /&gt; config-&amp;gt;group1MultiplexControl = kFLEXBUS_MultiplexGroup1_FB_ALE; /* FB_ALE */&lt;BR /&gt; config-&amp;gt;group2MultiplexControl = kFLEXBUS_MultiplexGroup2_FB_CS4; /* FB_CS4 */&lt;BR /&gt; config-&amp;gt;group3MultiplexControl = kFLEXBUS_MultiplexGroup3_FB_CS5; /* FB_CS5 */&lt;BR /&gt; config-&amp;gt;group4MultiplexControl = kFLEXBUS_MultiplexGroup4_FB_TBST; /* FB_TBST */&lt;BR /&gt; config-&amp;gt;group5MultiplexControl = kFLEXBUS_MultiplexGroup5_FB_TA; /* FB_TA */&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;The minmum time of FB5 shuld be&amp;nbsp;&amp;nbsp;0.5 ns.Is it the reasion to make it? How to adujst it?&lt;/P&gt;&lt;P&gt;Thanks and best regards!&lt;/P&gt;&lt;P&gt;zhai&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Feb 2017 09:00:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/Kinetis-Software-Development-Kit/How-to-use-freescale-k64f-flexbus/m-p/635529#M6821</guid>
      <dc:creator>zhailing</dc:creator>
      <dc:date>2017-02-27T09:00:38Z</dc:date>
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