topic Re: K64F DSPI Clock Glitch (KSDK SPI Master Driver) in Kinetis Software Development Kit

K64F DSPI Clock Glitch (KSDK SPI Master Driver)

JonSzymaniak — Mon, 24 Nov 2014 03:45:33 GMT

Hi there,

I'm just looking to test out some simple DSPI Master transfers (non-DMA operation) on the FRDM-K64F using the KSDK (1.0.0) Master peripheral driver.

The API seems pretty straight-forward. However, with in each byte in my transfers, there's a glitch between bit 0 and bit 7 of the following byte:

This only appears to happen for the kDspiClockPhase_FirstEdge clock phase option.

I was just curious if anyone else has run into this. The code's attached.

Cheers,

Jon

Original Attachment has been moved to: main.c.zip

Re: K64F DSPI Clock Glitch (KSDK SPI Master Driver)

JonSzymaniak — Mon, 24 Nov 2014 14:45:35 GMT

A colleague of mine kindly pointed out that I have overlooked the DSPI_DRV_MasterSetDelay() API function. Using this with the kDspiAfterTransfer option) has allowed me to introduce time between successive words within a transfer.

I'll have to take a look at the datasheet and the peripheral driver to understand why I needed to do this for kDspiClockPhase_FirstEdge, but not kDspiClockPhase_SecondEdge....will try to report back here, if anyone is interested.

Just as another minor note -- I see the data is idling high, hence that momentary spike between data byte 0 and data byte 1 in my previous screenshot.

- Jon

Re: K64F DSPI Clock Glitch (KSDK SPI Master Driver)

codylundie — Tue, 01 Mar 2016 18:29:18 GMT

I am experiencing the same behavior under the same conditions. Was DSPI_DRV_MasterSetDelay() the ultimate fix, or did you uncover anything else?