Slowing Down SDHC clock

neilporven — Thu, 09 Jun 2016 21:04:51 GMT

Hi everyone,

I keep having issues with my SDHC and reading from an SD card. I believe the issue has to do with

slowing down the clock.

I am working with a custom board, processor is the MK64F, I am using KDS 3.1.0 + KSDK 1.3.

The project is a bare bone, no PE, RTO, etc..... I am using FatFs + SDHC data logger demo

with KSDK by Jorge Gonzalez. The demo was meant to be used with the FRDM-K64F board

and changing the clock there to 400KHZ seems to work, but not on my custom board.

I noticed that in the fsl_sdhc_driver.c (FreeScale->KSDK_1.3.0->platform->drivers->src->sdhc),

exists a function called CLOCK_SYS_SetSdhcSrc(instance,kClockSdhcSrcPllFllSel)

the kClockSdhcSrcPllFllSel is a value passed to the SDHC clock to satisfy the register SIM_SOPT2->SDHCSRC,

which lets the SDHC clock know which clock to work from. I am trying to replace that value (kClockSdhcSrcPllFllSel )

with kClockSdhcSrcCoreSysClk in the function mentioned above, because I want to use 00 Core/system clock

as my setting for my custom board.

The issue I am experiencing is that if I physically change it in the function, when I step into the function and fall

in a deeper internal function, the value changes back to the kClockSdhcSrcPllFllSel setting originally there?????

How can I change the function to the settings I want?

Thank you,

Neil Porven

Re: Slowing Down SDHC clock

xiangjun_rong — Tue, 28 Jun 2016 08:13:06 GMT

Hi, Neil,

I am sorry for the delay.

Regarding your question, let's explain the SDHC clock source configuration. For K64, the SDHC module clock source is only defined in SIM_SOPT2 register.

The SDHCSRC bits in SIM_SOPT2 register specify the SDHC module clock source:

SDHCSRC bit:SDHC clock source select:

Selects the clock source for the SDHC clock .

00 Core/system clock.

01 MCGFLLCLK, or MCGPLLCLK, or IRC48M clock as selected by SOPT2[PLLFLLSEL].

10 OSCERCLK clock

11 External bypass clock (SDHC0_CLKIN)

Only when you set the SDHCSRC as 01 in binary, the PLLFLLSEL bits make sense, the bits can select MCGFLLCLK clock, MCGPLLCLK clock, IRC48 MHz clock.

PLLFLLSEL bits:PLL/FLL clock select

Selects the high frequency clock for various peripheral clocking options.

00 MCGFLLCLK clock

01 MCGPLLCLK clock

10 Reserved

11 IRC48 MHz clock

Regarding the core clock, pls refer to the file system_MK64F12.c, you can redefine the CLOCK_SETUP macro to select different core clock frequency.

for example

#define CLOCK_SETUP 1

This is the meaning of the degination:

/* Predefined clock setups

0 ... Default part configuration

Multipurpose Clock Generator (MCG) in FEI mode.

Reference clock source for MCG module: Slow internal reference clock

Core clock = 20.97152MHz

Bus clock = 20.97152MHz

1 ... Maximum achievable clock frequency configuration

Multipurpose Clock Generator (MCG) in PEE mode.

Reference clock source for MCG module: System oscillator 0 reference clock

Core clock = 120MHz

Bus clock = 60MHz

2 ... Chip internaly clocked, ready for Very Low Power Run mode.

Multipurpose Clock Generator (MCG) in BLPI mode.

Reference clock source for MCG module: Fast internal reference clock

Core clock = 4MHz

Bus clock = 4MHz

3 ... Chip externally clocked, ready for Very Low Power Run mode.

Multipurpose Clock Generator (MCG) in BLPE mode.

Reference clock source for MCG module: RTC oscillator reference clock

Core clock = 0.032768MHz

Bus clock = 0.032768MHz

4 ... USB clock setup

Multipurpose Clock Generator (MCG) in PEE mode.

Reference clock source for MCG module: System oscillator 0 reference clock

Core clock = 120MHz

Bus clock = 60MHz

Hope it can help you.

XiangJun rong

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