topic Re: CPU Clock configuration in Kinetis Design Studio

CPU Clock configuration

davidsherman — Wed, 04 Jun 2014 15:16:02 GMT

Hello, I'm trying to configure the clock for a Kinetis MKE06Z128 on the FRDM-KE06 board. I had an MQX-Lite application running using the default internal clock, but when I try to configure for the 8 MHz crystal, it doesn't work and the crystal is not oscillating. Is there a separate component I need to add to control the OSC module? I have these settings in the clock settings for the CPU module:

System Oscillator - checked

Clock Frequency - 8 MHz

Oscillator operating mode - low power

Clock source settings:

ICS mode - FEE

FLL output - 40 MHz (only option)

ICS output clock - 10 MHz (also tried 40 MHz, doesn't work)

I have enabled the SetClockConfiguration method under the CPU component.

Re: CPU Clock configuration

davidsherman — Wed, 04 Jun 2014 20:36:37 GMT

I've confirmed it, the code generated which configures the clocks has problems. If I try to configure for FBE mode operation using an 8MHz crystal, the OSC_CR value it comes up with is 0x0, which is wrong, and the ICS_C1 value it comes up with is 0xC2, which is also wrong. I'll try submitting a bug report, hopefully this will be fixed.

Edit: I have found specifically what's wrong. The CPU_Config.h that PE comes up with has the wrong values for CPU_ICS_C1_CONFIG_0, CPU_OSC_CR_CONFIG_0. Not just a little wrong, but not even close. Secondly, in CPU_Init.c, the initialization for CPU_ClockConfigDescriptors leaves out the initializer for OSC_CR_Value, so it will never populate the OSC_CR register properly.

If I try to configure the Kinetis for a 40 MHz core clock, 20 MHz bus clock, 40 MHz running off an 8 MHz external crystal in FEE mode, the correct values should be:

OSC_CR = 0xB4 (Oscillator enabled, Oscillator enabled in stop mode, Oscillator clock source selected, Oscillator high range enabled, low power mode enabled)

ISC_C1 = 0x18 (FLL output selected as clock source, Reference divider = 256, external reference selected for FLL, Internal reference clock disabled)

ISC_C2 = 0x00 (Divide clock by 1)

If I try the same settings in PE, here is what it comes up with;

OSC_CR = 0x14 ( oscillator disabled, oscillator clock source selected, oscillator high range enabled, low power mode enabled) - note that 0x0 is what actually gets written to OSC_CR.

ISC_C1 = 0x42 (Internal reference selected as clock source, reference divider = 32, external reference selected for FLL, Internal reference clock enabled)

ISC_C2 = 0x0 (divide clock by 1) - correct

Re: CPU Clock configuration

BlackNight — Fri, 06 Jun 2014 07:23:49 GMT

Hi David,

I have submitted a ticket (ENGR00317168) so hopefully this can be addressed.

Erich

Re: CPU Clock configuration

davidsherman — Sat, 07 Jun 2014 16:59:15 GMT

Thanks Erich, I appreciate it. I have submitted a ticket as well. FYI, CodeWarrior 10.6 has the same problem.

Re: CPU Clock configuration

ConstYu — Mon, 24 Oct 2016 02:42:37 GMT

Hi Eric,

I tried on my CW10.6, found the same issues, the problem is still remaining now. Can you help check whether this problem is fixed. Thanks.